diff --git a/artiq/coredevice/spi.py b/artiq/coredevice/spi.py
index 9069a40d6..5c2461216 100644
--- a/artiq/coredevice/spi.py
+++ b/artiq/coredevice/spi.py
@@ -95,7 +95,7 @@ class SPIMaster:
     def set_config(self, flags=0, write_freq=20*MHz, read_freq=20*MHz):
         """Set the configuration register.
 
-        * If ``config.cs_polarity`` == 0 (```cs`` active low, the default),
+        * If ``config.cs_polarity`` == 0 (``cs`` active low, the default),
           "``cs_n`` all deasserted" means "all ``cs_n`` bits high".
         * ``cs_n`` is not mandatory in the pads supplied to the gateware core.
           Framing and chip selection can also be handled independently