forked from M-Labs/artiq
phaser: false paths sys<->{jesd,phy.tx}
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9221a275cb
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174c4be218
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@ -451,7 +451,7 @@ class AD9154JESD(Module, AutoCSR):
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qpll = GTXQuadPLL(refclk, refclk_freq, linerate)
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self.submodules += qpll
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phys = []
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self.phys = []
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for i in range(4):
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phy = JESD204BPhyTX(
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qpll, platform.request("ad9154_jesd", i), fabric_freq)
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@ -459,9 +459,9 @@ class AD9154JESD(Module, AutoCSR):
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platform.add_period_constraint(phy.gtx.cd_tx.clk, 40*1e9/linerate)
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platform.add_false_path_constraints(self.cd_jesd.clk,
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phy.gtx.cd_tx.clk)
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phys.append(phy)
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self.phys.append(phy)
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to_jesd = ClockDomainsRenamer("jesd")
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self.submodules.core = to_jesd(JESD204BCoreTX(phys, settings,
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self.submodules.core = to_jesd(JESD204BCoreTX(self.phys, settings,
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converter_data_width=32))
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self.submodules.control = to_jesd(JESD204BCoreTXControl(self.core))
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@ -595,8 +595,12 @@ class Phaser(MiniSoC, AMPSoC):
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self.config["RTIO_FINE_TS_WIDTH"] = self.rtio.fine_ts_width
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk,
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self.rtio_crg.cd_rtio.clk)
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self.crg.cd_sys.clk, self.rtio_crg.cd_rtio.clk)
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, self.ad9154.jesd.cd_jesd.clk)
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for phy in self.ad9154.jesd.phys:
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platform.add_false_path_constraints(
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self.crg.cd_sys.clk, phy.gtx.cd_tx.clk)
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def main():
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