srenblad
/
artiq
forked from M-Labs/artiq
1
0
Fork 0
Code Pull Requests Activity

coredevice.spi: cleanup

This commit is contained in:
Robert Jördens 2016-02-29 19:48:26 +01:00
parent ecedbbef4c
commit 16537d347e
1 changed files with 8 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
artiq/coredevice/spi.py
View File

@ -1,4 +1,5 @@
from artiq.language.core import * from artiq.language.core import (kernel, portable, seconds_to_mu, now_mu,
delay_mu)
from artiq.language.units import MHz from artiq.language.units import MHz
from artiq.coredevice.rt2wb import rt2wb_write, rt2wb_read_sync from artiq.coredevice.rt2wb import rt2wb_write, rt2wb_read_sync
@ -83,6 +84,11 @@ class SPIMaster:
SPI_RT2WB_READ, int(2*self.ref_period_mu)) SPI_RT2WB_READ, int(2*self.ref_period_mu))
@kernel @kernel
def get_config_sync(self): def _get_config_sync(self):
return rt2wb_read_sync(now_mu(), self.channel, SPI_CONFIG_ADDR | return rt2wb_read_sync(now_mu(), self.channel, SPI_CONFIG_ADDR |
SPI_RT2WB_READ, int(2*self.ref_period_mu)) SPI_RT2WB_READ, int(2*self.ref_period_mu))
@kernel
def _get_xfer_sync(self):
return rt2wb_read_sync(now_mu(), self.channel, SPI_XFER_ADDR |
SPI_RT2WB_READ, int(2*self.ref_period_mu))