From 12b8598b84cfb36a294ef8cfcfbf97200b593577 Mon Sep 17 00:00:00 2001 From: Florent Kermarrec Date: Wed, 12 Oct 2016 15:59:27 +0200 Subject: [PATCH] stpl: fix byte ordering --- artiq/examples/phaser/repository/test_ad9154_stpl.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/artiq/examples/phaser/repository/test_ad9154_stpl.py b/artiq/examples/phaser/repository/test_ad9154_stpl.py index 3dc3acda0..4e892177c 100644 --- a/artiq/examples/phaser/repository/test_ad9154_stpl.py +++ b/artiq/examples/phaser/repository/test_ad9154_stpl.py @@ -27,8 +27,8 @@ class Test(EnvExperiment): AD9154_SHORT_TPL_DAC_SEL_SET(i) | AD9154_SHORT_TPL_SP_SEL_SET(0)) # set expected value - self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_2, data & 0xff) - self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_1, (data & 0xff00) >> 8) + self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_1, data & 0xff) + self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_2, (data & 0xff00) >> 8) # enable stpl self.ad9154.dac_write(AD9154_SHORT_TPL_TEST_0, AD9154_SHORT_TPL_TEST_EN_SET(1) |