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dds: fix phase computation. Closes #79.

This commit is contained in:
Sebastien Bourdeauducq 2015-08-27 11:09:33 +08:00
parent f07c7e9c6f
commit 0fe0f4d433
1 changed files with 3 additions and 3 deletions
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6
artiq/coredevice/dds.py
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@ -131,11 +131,11 @@ class _DDSGeneric:
"""
if phase_mode == _PHASE_MODE_DEFAULT:
phase_mode = self.phase_mode
syscall("dds_set", now_mu(), self.channel,
frequency, round(phase*2**self.pow_width), phase_mode)
syscall("dds_set", now_mu(), self.channel, frequency,
phase, phase_mode)
@kernel
def set(self, frequency, phase=0, phase_mode=_PHASE_MODE_DEFAULT):
def set(self, frequency, phase=0.0, phase_mode=_PHASE_MODE_DEFAULT):
"""Like ``set_mu``, but uses Hz and turns."""
self.set_mu(self.frequency_to_ftw(frequency),
self.turns_to_pow(phase), phase_mode)