forked from M-Labs/artiq
runtime/dds: fix AD9914 register initialization values
Thanks Raghavendra Srinivas for the help. Closes #114.
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1991b3c910
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@ -18,7 +18,7 @@
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/* DAC calibration takes max. 135us as per datasheet. Take a good margin. */
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#define DURATION_DAC_CAL (30000 << RTIO_FINE_TS_WIDTH)
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/* not counting final FUD */
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#define DURATION_INIT (8*DURATION_WRITE + DURATION_DAC_CAL)
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#define DURATION_INIT (10*DURATION_WRITE + DURATION_DAC_CAL)
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#define DURATION_PROGRAM (5*DURATION_WRITE) /* not counting FUD */
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#else
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@ -79,6 +79,8 @@ void dds_init(long long int timestamp, int channel)
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#ifdef DDS_AD9914
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DDS_WRITE(DDS_CFR1H, 0x0000); /* Enable cosine output */
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DDS_WRITE(DDS_CFR2L, 0x8900); /* Enable matched latency */
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DDS_WRITE(DDS_CFR2H, 0x0080); /* Enable profile mode */
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DDS_WRITE(DDS_ASF, 0x0fff); /* Set amplitude to maximum */
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DDS_WRITE(DDS_CFR4H, 0x0105); /* Enable DAC calibration */
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DDS_WRITE(DDS_FUD, 0);
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now += DURATION_DAC_CAL;
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@ -35,6 +35,7 @@
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#define DDS_FTWL 0x2d
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#define DDS_FTWH 0x2f
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#define DDS_POW 0x31
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#define DDS_ASF 0x33
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#define DDS_FUD 0x80
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#define DDS_GPIO 0x81
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#endif
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@ -239,6 +239,8 @@ static void ddsinit(void)
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brg_ddsreset();
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brg_ddswrite(DDS_CFR1H, 0x0000); /* Enable cosine output */
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brg_ddswrite(DDS_CFR2L, 0x8900); /* Enable matched latency */
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brg_ddswrite(DDS_CFR2H, 0x0080); /* Enable profile mode */
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brg_ddswrite(DDS_ASF, 0x0fff); /* Set amplitude to maximum */
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brg_ddswrite(DDS_CFR4H, 0x0105); /* Enable DAC calibration */
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brg_ddswrite(DDS_FUD, 0);
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t = clock_get_ms();
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