forked from M-Labs/artiq
sayma_amc2: select filtered clock from Si5324
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@ -381,6 +381,8 @@ class Satellite(BaseSoC, RTMCommon):
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6)
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if self.hw_rev == "v2.0":
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self.comb += platform.request("filtered_clk_sel").eq(1)
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self.submodules.siphaser = SiPhaser7Series(
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self.submodules.siphaser = SiPhaser7Series(
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si5324_clkin=platform.request("si5324_clkin"),
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si5324_clkin=platform.request("si5324_clkin"),
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rx_synchronizer=self.rx_synchronizer,
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rx_synchronizer=self.rx_synchronizer,
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