From 0cf8a46bbdd90f0e5d50e56fab9b00a97342ea95 Mon Sep 17 00:00:00 2001 From: Sebastien Bourdeauducq Date: Fri, 4 Oct 2019 21:28:26 +0800 Subject: [PATCH] sayma_amc2: select filtered clock from Si5324 --- artiq/gateware/targets/sayma_amc.py | 2 ++ 1 file changed, 2 insertions(+) diff --git a/artiq/gateware/targets/sayma_amc.py b/artiq/gateware/targets/sayma_amc.py index 011788c55..12ff2825a 100755 --- a/artiq/gateware/targets/sayma_amc.py +++ b/artiq/gateware/targets/sayma_amc.py @@ -381,6 +381,8 @@ class Satellite(BaseSoC, RTMCommon): ] self.config["RTIO_FREQUENCY"] = str(rtio_clk_freq/1e6) + if self.hw_rev == "v2.0": + self.comb += platform.request("filtered_clk_sel").eq(1) self.submodules.siphaser = SiPhaser7Series( si5324_clkin=platform.request("si5324_clkin"), rx_synchronizer=self.rx_synchronizer,