forked from M-Labs/artiq
1
0
Fork 0

board_misoc: reuse riscv dir for comm & kernel

This commit is contained in:
occheung 2021-11-08 12:51:50 +08:00 committed by Sébastien Bourdeauducq
parent cb247f235f
commit 0898e101e2
7 changed files with 4 additions and 7 deletions

View File

@ -1,19 +1,16 @@
extern crate build_misoc; extern crate build_misoc;
extern crate cc; extern crate cc;
use std::env;
use std::path::Path; use std::path::Path;
fn main() { fn main() {
build_misoc::cfg(); build_misoc::cfg();
let triple = env::var("TARGET").unwrap(); let vectors_path = "riscv32/vectors.S";
let arch = triple.split("-").next().unwrap();
let vectors_path = Path::new(arch).join("vectors.S");
println!("cargo:rerun-if-changed={}", vectors_path.to_str().unwrap()); println!("cargo:rerun-if-changed={}", vectors_path);
cc::Build::new() cc::Build::new()
.flag("--target=riscv32-unknown-elf") .flag("--target=riscv32-unknown-elf")
.file(vectors_path) .file(Path::new(vectors_path))
.compile("vectors"); .compile("vectors");
} }

View File

@ -8,7 +8,7 @@ extern crate log;
extern crate smoltcp; extern crate smoltcp;
#[cfg(target_arch = "riscv32")] #[cfg(target_arch = "riscv32")]
#[path = "riscv32ima/mod.rs"] #[path = "riscv32/mod.rs"]
mod arch; mod arch;
#[cfg(target_arch = "riscv32")] #[cfg(target_arch = "riscv32")]