drtio: remote resets

artiq/examples/drtio/repository/blink_forever.py

@@ -8,8 +8,7 @@ class BlinkForever(EnvExperiment):
 
     @kernel
     def run(self):
-        #self.core.reset()
+        self.core.reset()
-        self.core.break_realtime()
 
         while True:
             for led in self.leds:

artiq/examples/drtio/repository/pulse_rate.py

@@ -8,8 +8,7 @@ class PulseRate(EnvExperiment):
 
     @kernel
     def run(self):
-        #self.core.reset()
+        self.core.reset()
-        self.core.break_realtime()
 
         dt = self.core.seconds_to_mu(300*ns)
         while True:

artiq/gateware/drtio/core.py

@@ -27,17 +27,16 @@ class DRTIOSatellite(Module):
         self.submodules.rt_packets = ClockDomainsRenamer("rtio")(
             rt_packets.RTPacketSatellite(link_layer_sync))
 
-        self.submodules.iot = ClockDomainsRenamer("rtio")(
+        self.submodules.iot = ClockDomainsRenamer("rio")(
             iot.IOT(self.rt_packets, channels, fine_ts_width, full_ts_width))
 
-        # TODO: remote resets
         self.clock_domains.cd_rio = ClockDomain()
         self.clock_domains.cd_rio_phy = ClockDomain()
         self.comb += [
             self.cd_rio.clk.eq(ClockSignal("rtio")),
-            self.cd_rio.rst.eq(ResetSignal("rtio", allow_reset_less=True)),
+            self.cd_rio.rst.eq(self.rt_packets.reset),
             self.cd_rio_phy.clk.eq(ClockSignal("rtio")),
-            self.cd_rio_phy.rst.eq(ResetSignal("rtio", allow_reset_less=True)),
+            self.cd_rio_phy.rst.eq(self.rt_packets.reset_phy),
         ]
 
         self.submodules.aux_controller = aux_controller.AuxController(

artiq/gateware/drtio/rt_controller.py

@@ -54,6 +54,19 @@ class RTController(Module):
             If(self.csrs.set_time.re, rt_packets.set_time_stb.eq(1))
         ]
 
+        # reset
+        self.sync += [
+            If(rt_packets.reset_ack, rt_packets.reset_stb.eq(0)),
+            If(self.cri.cmd == cri.commands["reset"],
+                rt_packets.reset_stb.eq(1),
+                rt_packets.reset_phy.eq(0)
+            ),
+            If(self.cri.cmd == cri.commands["reset_phy"],
+                rt_packets.reset_stb.eq(1),
+                rt_packets.reset_phy.eq(1)
+            ),
+        ]
+
         # remote channel status cache
         fifo_spaces_mem = Memory(16, channel_count)
         fifo_spaces = fifo_spaces_mem.get_port(write_capable=True)

artiq/gateware/drtio/rt_packets.py

@@ -34,6 +34,7 @@ def get_m2s_layouts(alignment):
     plm = PacketLayoutManager(alignment)
     plm.add_type("echo_request")
     plm.add_type("set_time", ("timestamp", 64))
+    plm.add_type("reset", ("phy", 1))
     plm.add_type("write", ("timestamp", 64),
                           ("channel", 16),
                           ("address", 16),
@@ -178,7 +179,10 @@ class RTPacketSatellite(Module):
     def __init__(self, link_layer):
         self.tsc_load = Signal()
         self.tsc_value = Signal(64)
-        
+
+        self.reset = Signal(reset=1)
+        self.reset_phy = Signal(reset=1)
+
         self.fifo_space_channel = Signal(16)
         self.fifo_space_update = Signal()
         self.fifo_space = Signal(16)
@@ -240,6 +244,13 @@ class RTPacketSatellite(Module):
                 rx_dp.packet_as["write"].short_data)
         ]
 
+        reset = Signal()
+        reset_phy = Signal()
+        self.sync += [
+            self.reset.eq(reset),
+            self.reset_phy.eq(reset_phy)
+        ]
+
         rx_fsm = FSM(reset_state="INPUT")
         self.submodules += rx_fsm
 
@@ -252,6 +263,7 @@ class RTPacketSatellite(Module):
                         # mechanism
                         rx_plm.types["echo_request"]: echo_req.eq(1),
                         rx_plm.types["set_time"]: NextState("SET_TIME"),
+                        rx_plm.types["reset"]: NextState("RESET"),
                         rx_plm.types["write"]: NextState("WRITE"),
                         rx_plm.types["fifo_space_request"]:
                             NextState("FIFO_SPACE"),
@@ -266,6 +278,14 @@ class RTPacketSatellite(Module):
             self.tsc_load.eq(1),
             NextState("INPUT")
         )
+        rx_fsm.act("RESET",
+            If(rx_dp.packet_as["reset"].phy,
+                reset_phy.eq(1)
+            ).Else(
+                reset.eq(1)
+            ),
+            NextState("INPUT")
+        )
         rx_fsm.act("WRITE",
             self.write_stb.eq(1),
             NextState("INPUT")
@@ -401,6 +421,11 @@ class RTPacketMaster(Module):
         # a set_time request pending
         self.tsc_value = Signal(64)
 
+        # reset interface
+        self.reset_stb = Signal()
+        self.reset_ack = Signal()
+        self.reset_phy = Signal()
+
         # errors
         self.error_not = Signal()
         self.error_not_ack = Signal()
@@ -441,6 +466,13 @@ class RTPacketMaster(Module):
             self.set_time_stb, self.set_time_ack, None,
             set_time_stb, set_time_ack, None)
 
+        reset_stb = Signal()
+        reset_ack = Signal()
+        reset_phy = Signal()
+        self.submodules += _CrossDomainRequest("rtio",
+            self.reset_stb, self.reset_ack, self.reset_phy,
+            reset_stb, reset_ack, reset_phy)
+
         echo_stb = Signal()
         echo_ack = Signal()
         self.submodules += _CrossDomainRequest("rtio",
@@ -496,6 +528,8 @@ class RTPacketMaster(Module):
                 ).Elif(set_time_stb,
                     tsc_value_load.eq(1),
                     NextState("SET_TIME")
+                ).Elif(reset_stb,
+                    NextState("RESET")
                 )
             )
         )
@@ -523,6 +557,14 @@ class RTPacketMaster(Module):
                 NextState("IDLE_WRITE")
             )
         )
+        tx_fsm.act("RESET",
+            tx_dp.send("reset", phy=reset_phy),
+            tx_dp.stb.eq(1),
+            If(tx_dp.done,
+                reset_ack.eq(1),
+                NextState("IDLE_WRITE")
+            )
+        )
 
         # RX FSM
         rx_fsm = ClockDomainsRenamer("rtio_rx")(FSM(reset_state="INPUT"))