forked from M-Labs/artiq
rtio: use only CRI commands for rio/rio_phy resets
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d400c81cb2
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@ -301,12 +301,10 @@ class Core(Module):
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]
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self.comb += self.cd_rio.clk.eq(ClockSignal("rtio"))
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self.specials += AsyncResetSynchronizer(
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self.cd_rio,
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cmd_reset | ResetSignal("rtio", allow_reset_less=True))
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self.cd_rio, cmd_reset)
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self.comb += self.cd_rio_phy.clk.eq(ClockSignal("rtio"))
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self.specials += AsyncResetSynchronizer(
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self.cd_rio_phy,
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cmd_reset_phy | ResetSignal("rtio", allow_reset_less=True))
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self.cd_rio_phy, cmd_reset_phy)
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# Managers
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self.submodules.counter = RTIOCounter(len(self.cri.o_timestamp) - fine_ts_width)
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