forked from M-Labs/artiq
drtio: remote resets
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9941f3557d
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07f2d84275
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@ -8,8 +8,7 @@ class BlinkForever(EnvExperiment):
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@kernel
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def run(self):
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#self.core.reset()
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self.core.break_realtime()
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self.core.reset()
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while True:
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for led in self.leds:
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@ -8,8 +8,7 @@ class PulseRate(EnvExperiment):
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@kernel
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def run(self):
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#self.core.reset()
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self.core.break_realtime()
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self.core.reset()
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dt = self.core.seconds_to_mu(300*ns)
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while True:
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@ -27,17 +27,16 @@ class DRTIOSatellite(Module):
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self.submodules.rt_packets = ClockDomainsRenamer("rtio")(
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rt_packets.RTPacketSatellite(link_layer_sync))
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self.submodules.iot = ClockDomainsRenamer("rtio")(
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self.submodules.iot = ClockDomainsRenamer("rio")(
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iot.IOT(self.rt_packets, channels, fine_ts_width, full_ts_width))
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# TODO: remote resets
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self.clock_domains.cd_rio = ClockDomain()
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self.clock_domains.cd_rio_phy = ClockDomain()
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self.comb += [
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self.cd_rio.clk.eq(ClockSignal("rtio")),
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self.cd_rio.rst.eq(ResetSignal("rtio", allow_reset_less=True)),
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self.cd_rio.rst.eq(self.rt_packets.reset),
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self.cd_rio_phy.clk.eq(ClockSignal("rtio")),
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self.cd_rio_phy.rst.eq(ResetSignal("rtio", allow_reset_less=True)),
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self.cd_rio_phy.rst.eq(self.rt_packets.reset_phy),
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]
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self.submodules.aux_controller = aux_controller.AuxController(
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@ -54,6 +54,19 @@ class RTController(Module):
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If(self.csrs.set_time.re, rt_packets.set_time_stb.eq(1))
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]
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# reset
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self.sync += [
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If(rt_packets.reset_ack, rt_packets.reset_stb.eq(0)),
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If(self.cri.cmd == cri.commands["reset"],
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rt_packets.reset_stb.eq(1),
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rt_packets.reset_phy.eq(0)
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),
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If(self.cri.cmd == cri.commands["reset_phy"],
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rt_packets.reset_stb.eq(1),
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rt_packets.reset_phy.eq(1)
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),
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]
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# remote channel status cache
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fifo_spaces_mem = Memory(16, channel_count)
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fifo_spaces = fifo_spaces_mem.get_port(write_capable=True)
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@ -34,6 +34,7 @@ def get_m2s_layouts(alignment):
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plm = PacketLayoutManager(alignment)
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plm.add_type("echo_request")
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plm.add_type("set_time", ("timestamp", 64))
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plm.add_type("reset", ("phy", 1))
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plm.add_type("write", ("timestamp", 64),
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("channel", 16),
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("address", 16),
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@ -178,7 +179,10 @@ class RTPacketSatellite(Module):
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def __init__(self, link_layer):
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self.tsc_load = Signal()
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self.tsc_value = Signal(64)
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self.reset = Signal(reset=1)
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self.reset_phy = Signal(reset=1)
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self.fifo_space_channel = Signal(16)
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self.fifo_space_update = Signal()
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self.fifo_space = Signal(16)
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@ -240,6 +244,13 @@ class RTPacketSatellite(Module):
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rx_dp.packet_as["write"].short_data)
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]
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reset = Signal()
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reset_phy = Signal()
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self.sync += [
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self.reset.eq(reset),
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self.reset_phy.eq(reset_phy)
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]
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rx_fsm = FSM(reset_state="INPUT")
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self.submodules += rx_fsm
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@ -252,6 +263,7 @@ class RTPacketSatellite(Module):
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# mechanism
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rx_plm.types["echo_request"]: echo_req.eq(1),
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rx_plm.types["set_time"]: NextState("SET_TIME"),
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rx_plm.types["reset"]: NextState("RESET"),
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rx_plm.types["write"]: NextState("WRITE"),
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rx_plm.types["fifo_space_request"]:
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NextState("FIFO_SPACE"),
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@ -266,6 +278,14 @@ class RTPacketSatellite(Module):
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self.tsc_load.eq(1),
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NextState("INPUT")
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)
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rx_fsm.act("RESET",
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If(rx_dp.packet_as["reset"].phy,
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reset_phy.eq(1)
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).Else(
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reset.eq(1)
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),
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NextState("INPUT")
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)
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rx_fsm.act("WRITE",
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self.write_stb.eq(1),
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NextState("INPUT")
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@ -401,6 +421,11 @@ class RTPacketMaster(Module):
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# a set_time request pending
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self.tsc_value = Signal(64)
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# reset interface
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self.reset_stb = Signal()
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self.reset_ack = Signal()
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self.reset_phy = Signal()
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# errors
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self.error_not = Signal()
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self.error_not_ack = Signal()
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@ -441,6 +466,13 @@ class RTPacketMaster(Module):
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self.set_time_stb, self.set_time_ack, None,
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set_time_stb, set_time_ack, None)
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reset_stb = Signal()
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reset_ack = Signal()
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reset_phy = Signal()
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self.submodules += _CrossDomainRequest("rtio",
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self.reset_stb, self.reset_ack, self.reset_phy,
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reset_stb, reset_ack, reset_phy)
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echo_stb = Signal()
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echo_ack = Signal()
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self.submodules += _CrossDomainRequest("rtio",
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@ -496,6 +528,8 @@ class RTPacketMaster(Module):
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).Elif(set_time_stb,
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tsc_value_load.eq(1),
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NextState("SET_TIME")
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).Elif(reset_stb,
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NextState("RESET")
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)
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)
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)
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@ -523,6 +557,14 @@ class RTPacketMaster(Module):
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NextState("IDLE_WRITE")
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)
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)
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tx_fsm.act("RESET",
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tx_dp.send("reset", phy=reset_phy),
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tx_dp.stb.eq(1),
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If(tx_dp.done,
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reset_ack.eq(1),
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NextState("IDLE_WRITE")
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)
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)
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# RX FSM
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rx_fsm = ClockDomainsRenamer("rtio_rx")(FSM(reset_state="INPUT"))
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