forked from M-Labs/artiq
shuttler: impl general reg access
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e443e06e62
commit
06426e0ed9
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@ -170,44 +170,47 @@ class ADC:
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@kernel
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@kernel
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def read_id(self) -> TInt32:
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def read_id(self) -> TInt32:
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self.bus.set_config_mu(
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ADC_SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
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24, ADC_SPI_DIV, ADC_CS)
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self.bus.write(0x47 << 24)
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return (self.bus.read() & 0xFFFF)
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@kernel
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@kernel
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def read_ch(self, channel: TInt32) -> TFloat:
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def read8(self, addr: TInt32) -> TInt32:
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# Always configure Profile 0
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self.bus.set_config_mu(
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ADC_SPI_CONFIG | spi.SPI_END, 24, ADC_SPI_DIV, ADC_CS)
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self.bus.write(0x10 << 24 | (0x8000 | ((channel * 2 + 1) << 4)) << 8)
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# Configure Setup 0
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# Input buffer must be enabled to use REF pins correctly
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self.bus.set_config_mu(
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ADC_SPI_CONFIG | spi.SPI_END, 24, ADC_SPI_DIV, ADC_CS)
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self.bus.write((0x20 << 24) | (0x1300 << 8))
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# Trigger single conversion
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self.bus.set_config_mu(
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ADC_SPI_CONFIG, 24, ADC_SPI_DIV, ADC_CS)
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self.bus.write((0x01 << 24) | (0x8010 << 8))
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self.bus.set_config_mu(
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ADC_SPI_CONFIG | spi.SPI_INPUT, 16, ADC_SPI_DIV, ADC_CS)
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self.bus.write(0x40 << 24)
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while self.bus.read() & 0x80:
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delay(10*us)
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self.bus.write(0x40 << 24)
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delay(10*us)
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self.bus.set_config_mu(
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self.bus.set_config_mu(
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ADC_SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
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ADC_SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
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32, ADC_SPI_DIV, ADC_CS)
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16, SPIT_ADC_RD, CS_ADC)
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self.bus.write(0x44 << 24)
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self.bus.write((addr | 0x40) << 24)
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return self.bus.read() & 0xff
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adc_code = self.bus.read() & 0xFFFFFF
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@kernel
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def read16(self, addr: TInt32) -> TInt32:
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self.bus.set_config_mu(
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ADC_SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
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24, SPIT_ADC_RD, CS_ADC)
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self.bus.write((addr | 0x40) << 24)
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return self.bus.read() & 0xffff
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@kernel
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def read24(self, addr: TInt32) -> TInt32:
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self.bus.set_config_mu(
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ADC_SPI_CONFIG | spi.SPI_END | spi.SPI_INPUT,
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32, SPIT_ADC_RD, CS_ADC)
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self.bus.write((addr | 0x40) << 24)
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return self.bus.read() & 0xffffff
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@kernel
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def write8(self, addr: TInt32, data: TInt32):
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self.bus.set_config_mu(
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ADC_SPI_CONFIG | spi.SPI_END, 16, SPIT_ADC_WR, CS_ADC)
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self.bus.write(addr << 24 | (data & 0xff) << 16)
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@kernel
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def write16(self, addr: TInt32, data: TInt32):
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self.bus.set_config_mu(
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ADC_SPI_CONFIG | spi.SPI_END, 24, SPIT_ADC_WR, CS_ADC)
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self.bus.write(addr << 24 | (data & 0xffff) << 8)
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@kernel
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def write24(self, addr: TInt32, data: TInt32):
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self.bus.set_config_mu(
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ADC_SPI_CONFIG | spi.SPI_END, 32, SPIT_ADC_WR, CS_ADC)
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self.bus.write(addr << 24 | (data & 0xffffff))
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return ((adc_code / (1 << 23)) - 1) * 2.5 / 0.1
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return ((adc_code / (1 << 23)) - 1) * 2.5 / 0.1
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@kernel
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@kernel
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