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wrpll: update OBUFDS_GTE2 comment 

Seems O can fan out simultaneously to transceiver and fabric.
Kasli is using ODIV2 for no particular reason.
This commit is contained in:
Sebastien Bourdeauducq 2019-12-09 11:57:33 +08:00
parent 4148efd2ee
commit 05e2e1899a
1 changed files with 2 additions and 5 deletions
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7
artiq/gateware/drtio/wrpll/ddmtd.py
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@ -27,12 +27,9 @@ class DDMTDSamplerGTP(Module):
self.rec_clk = Signal() self.rec_clk = Signal()
self.main_xo = Signal() self.main_xo = Signal()
# Getting the main XO signal from IBUFDS_GTE2 is problematic because: # Getting the main XO signal from IBUFDS_GTE2 is problematic because
# 1. the clock gets divided by 2 # the transceiver PLL craps out if an improper clock signal is applied,
# 2. the transceiver PLL craps out if an improper clock signal is applied,
# so we are disabling the buffer until the clock is stable. # so we are disabling the buffer until the clock is stable.
# 3. UG482 says "The O and ODIV2 outputs are not phase matched to each other",
# which may or may not be a problem depending on what it actually means.
main_xo_se = Signal() main_xo_se = Signal()
self.specials += [ self.specials += [
Instance("IBUFDS", Instance("IBUFDS",