forked from M-Labs/artiq
parent
5c3e834c4d
commit
041dc0f64a
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@ -85,12 +85,11 @@ class UltrascaleTX(Module, AutoCSR):
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phy.transmitter.cd_tx.clk)
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phys.append(phy)
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to_jesd = ClockDomainsRenamer("jesd")
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self.submodules.core = core = to_jesd(JESD204BCoreTX(
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phys, settings, converter_data_width=64))
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self.submodules.control = control = to_jesd(JESD204BCoreTXControl(core))
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core.register_jsync(platform.request("dac_sync", dac))
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core.register_jref(jesd_crg.jref)
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self.submodules.core = JESD204BCoreTX(
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phys, settings, converter_data_width=64)
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self.submodules.control = JESD204BCoreTXControl(self.core)
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self.core.register_jsync(platform.request("dac_sync", dac))
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self.core.register_jref(jesd_crg.jref)
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# This assumes:
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@ -16,7 +16,7 @@ requirements:
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- setuptools 33.1.1
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- migen 0.7 py35_73+gitbef9dea
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- misoc 0.11 py35_29+git57ebe119
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- jesd204b 0.9
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- jesd204b 0.10
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- microscope
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- binutils-or1k-linux >=2.27
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- llvm-or1k 6.0.0
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