From 041dc0f64a1c4ca65c165eac2c337fc2f11d2d18 Mon Sep 17 00:00:00 2001
From: Sebastien Bourdeauducq <sb@m-labs.hk>
Date: Fri, 17 Aug 2018 22:50:07 +0800
Subject: [PATCH] jesd204: update core to v0.10

Closes #727
Closes #1127
---
 artiq/gateware/jesd204_tools.py | 11 +++++------
 conda/artiq-dev/meta.yaml       |  2 +-
 2 files changed, 6 insertions(+), 7 deletions(-)

diff --git a/artiq/gateware/jesd204_tools.py b/artiq/gateware/jesd204_tools.py
index 167a05f3a..cdba0f7f6 100644
--- a/artiq/gateware/jesd204_tools.py
+++ b/artiq/gateware/jesd204_tools.py
@@ -85,12 +85,11 @@ class UltrascaleTX(Module, AutoCSR):
                 phy.transmitter.cd_tx.clk)
             phys.append(phy)
 
-        to_jesd = ClockDomainsRenamer("jesd")
-        self.submodules.core = core = to_jesd(JESD204BCoreTX(
-            phys, settings, converter_data_width=64))
-        self.submodules.control = control = to_jesd(JESD204BCoreTXControl(core))
-        core.register_jsync(platform.request("dac_sync", dac))
-        core.register_jref(jesd_crg.jref)
+        self.submodules.core = JESD204BCoreTX(
+            phys, settings, converter_data_width=64)
+        self.submodules.control = JESD204BCoreTXControl(self.core)
+        self.core.register_jsync(platform.request("dac_sync", dac))
+        self.core.register_jref(jesd_crg.jref)
 
 
 # This assumes:
diff --git a/conda/artiq-dev/meta.yaml b/conda/artiq-dev/meta.yaml
index e9f878df5..488e4f40d 100644
--- a/conda/artiq-dev/meta.yaml
+++ b/conda/artiq-dev/meta.yaml
@@ -16,7 +16,7 @@ requirements:
     - setuptools 33.1.1
     - migen 0.7 py35_73+gitbef9dea
     - misoc 0.11 py35_29+git57ebe119
-    - jesd204b 0.9
+    - jesd204b 0.10
     - microscope
     - binutils-or1k-linux >=2.27
     - llvm-or1k 6.0.0