forked from M-Labs/artiq
drtio: simple fixes
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parent
c39987b617
commit
029e0d95b7
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@ -2,7 +2,7 @@ from types import SimpleNamespace
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from migen import *
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from artiq.gateware.drtio import link_layer, rt_packets, iot, bus_interface
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from artiq.gateware.drtio import link_layer, rt_packets, iot, rt_controller
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class DRTIOSatellite(Module):
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@ -1,4 +1,5 @@
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from migen import *
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from migen.genlib.cdc import MultiReg
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from misoc.interconnect.csr import *
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@ -40,15 +41,15 @@ class RTController(Module):
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self.sync += If(self.kcsrs.counter_update.re,
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self.kcsrs.counter.status.eq(self.counter.value_sys))
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tsc_correction = Signal(64)
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self.specials += MultiReg(self.tsc_correction.storage, tsc_correction)
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self.specials += MultiReg(self.kcsrs.tsc_correction.storage, tsc_correction)
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self.comb += [
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rt_packets.tsc_value.eq(
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self.counter.value_rtio + tsc_correction),
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self.set_time.value.eq(rt_packets.set_time_stb)
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self.kcsrs.set_time.r.eq(rt_packets.set_time_stb)
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]
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self.sync += [
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If(rt_packets.set_time_ack, rt_packets.set_time_stb.eq(0)),
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If(self.set_time_stb.re, rt_packets.set_time_stb.eq(1))
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If(self.kcsrs.set_time.re, rt_packets.set_time_stb.eq(1))
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]
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fifo_spaces_mem = Memory(16, channel_count)
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@ -62,14 +63,14 @@ class RTController(Module):
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self.comb += [
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fifo_spaces.adr.eq(self.kcsrs.chan_sel.storage),
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last_timestamps.adr.eq(self.kcsrs.chan_sel.storage),
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last_timestamps.dat_w.eq(self.kcsrs.timestamp.storage),
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last_timestamps.dat_w.eq(self.kcsrs.o_timestamp.storage),
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rt_packets.write_channel.eq(self.kcsrs.chan_sel.storage),
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rt_packets.write_address.eq(self.kcsrs.o_address.storage),
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rt_packets.write_data.eq(self.kcsrs.o_data.storage),
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If(rt_packets_fifo_request,
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rt_packets.write_timestamp.eq(0xffff000000000000)
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).Else(
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rt_packets.write_timestamp.eq(self.o_timestamp.storage)
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rt_packets.write_timestamp.eq(self.kcsrs.o_timestamp.storage)
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)
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]
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@ -85,21 +86,21 @@ class RTController(Module):
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underflow_set = Signal()
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self.sync += [
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If(self.kcsrs.o_underflow_reset.re, status_underflow.eq(0)),
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If(self.kcsrs.o_sequence_error_reset, status_sequence_error.eq(0)),
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If(self.kcsrs.o_sequence_error_reset.re, status_sequence_error.eq(0)),
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If(underflow_set, status_underflow.eq(1)),
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If(sequence_error_set, status_sequence_error.eq(1)),
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]
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# TODO: collision, replace, busy
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cond_sequence_error = self.o_timestamp.storage < last_timestamps.dat_r
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cond_underflow = (self.o_timestamp.storage - self.kcsrs.underflow_margin.storage
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cond_sequence_error = self.kcsrs.o_timestamp.storage < last_timestamps.dat_r
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cond_underflow = (self.kcsrs.o_timestamp.storage - self.kcsrs.underflow_margin.storage
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< self.counter.value_sys)
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cond_fifo_emptied = ((last_timestamps.dat_r
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< self.counter.value_sys - self.kcsrs.underflow_margin.storage)
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& (last_timestamps.dat_r != 0))
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fsm.act("IDLE",
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If(self.o_we.re,
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If(self.kcsrs.o_we.re,
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If(cond_sequence_error,
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sequence_error_set.eq(1)
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).Elif(cond_underflow,
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@ -108,7 +109,7 @@ class RTController(Module):
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NextState("WRITE")
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)
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),
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If(self.get_fifo_space.re,
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If(self.kcsrs.get_fifo_space.re,
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NextState("GET_FIFO_SPACE")
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)
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)
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@ -142,9 +143,9 @@ class RTController(Module):
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status_wait.eq(1),
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fifo_spaces.dat_w.eq(rt_packets.fifo_space),
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fifo_spaces.we.eq(1),
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fifo_space_not_ack.eq(1),
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rt_packets.fifo_space_not_ack.eq(1),
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If(rt_packets.fifo_space_not,
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If(rt_packets.fifo_spaces > 0,
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If(rt_packets.fifo_space > 0,
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NextState("IDLE")
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).Else(
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NextState("GET_FIFO_SPACE")
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@ -418,7 +418,7 @@ class RTPacketMaster(Module):
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wfifo.din.eq(Cat(self.write_timestamp, self.write_channel,
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self.write_address, self.write_data)),
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Cat(write_timestamp, write_channel,
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write_address, write_data).eq(fifo.dout)
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write_address, write_data).eq(wfifo.dout)
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]
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fifo_space_not = Signal()
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