forked from M-Labs/zynq-rs
57 lines
1.6 KiB
Rust
57 lines
1.6 KiB
Rust
#[allow(unused)]
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use crate::{register, register_bit, register_bits, regs::RegisterRW};
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pub enum PllSource {
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IoPll = 0b00,
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ArmPll = 0b10,
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DdrPll = 0b11,
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}
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register!(uart_clk_ctrl, UartClkCtrl, RW, u32);
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register_bit!(uart_clk_ctrl, clkact0, 0);
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register_bit!(uart_clk_ctrl, clkact1, 1);
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register_bits!(uart_clk_ctrl, divisor, u8, 8, 13);
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register_bits!(uart_clk_ctrl, srcsel, u8, 4, 5);
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impl UartClkCtrl {
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const ADDR: *mut Self = 0xF8000154 as *mut _;
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pub fn new() -> &'static mut Self {
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unsafe { &mut *Self::ADDR }
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}
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pub fn enable_uart0(&self) {
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self.modify(|_, w| {
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// a. Clock divisor, slcr.UART_CLK_CTRL[DIVISOR] = 0x14.
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// b. Select the IO PLL, slcr.UART_CLK_CTRL[SRCSEL] = 0.
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// c. Enable the UART 0 Reference clock, slcr.UART_CLK_CTRL [CLKACT0] = 1.
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w.divisor(0x14)
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.srcsel(PllSource::IoPll as u8)
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.clkact0(true)
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})
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}
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}
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register!(uart_rst_ctrl, UartRstCtrl, RW, u32);
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register_bit!(uart_rst_ctrl, uart0_ref_rst, 3);
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register_bit!(uart_rst_ctrl, uart1_ref_rst, 2);
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register_bit!(uart_rst_ctrl, uart0_cpu1x_rst, 1);
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register_bit!(uart_rst_ctrl, uart1_cpu1x_rst, 0);
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impl UartRstCtrl {
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const ADDR: *mut Self = 0xF8000228 as *mut _;
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pub fn new() -> &'static mut Self {
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unsafe { &mut *Self::ADDR }
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}
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pub fn reset_uart0(&self) {
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self.modify(|_, w| w.uart0_ref_rst(true));
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self.modify(|_, w| w.uart0_ref_rst(false));
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}
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pub fn reset_uart1(&self) {
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self.modify(|_, w| w.uart1_ref_rst(true));
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self.modify(|_, w| w.uart1_ref_rst(false));
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}
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}
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