forked from M-Labs/zynq-rs
98 lines
2.2 KiB
Rust
98 lines
2.2 KiB
Rust
use bit_field::BitField;
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use super::PhyRegister;
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#[derive(Clone, Copy, Debug)]
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/// Basic Mode Control Register
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pub struct Control(pub u16);
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impl Control {
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pub fn speed1(&self) -> bool {
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self.0.get_bit(6)
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}
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pub fn set_speed1(mut self, value: bool) -> Self {
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self.0.set_bit(6, value);
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self
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}
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pub fn collision_test(&self) -> bool {
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self.0.get_bit(7)
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}
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pub fn set_collision_test(mut self, value: bool) -> Self {
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self.0.set_bit(7, value);
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self
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}
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pub fn duplex(&self) -> bool {
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self.0.get_bit(8)
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}
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pub fn set_duplex(mut self, value: bool) -> Self {
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self.0.set_bit(8, value);
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self
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}
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pub fn restart_autoneg(&self) -> bool {
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self.0.get_bit(9)
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}
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pub fn set_restart_autoneg(mut self, value: bool) -> Self {
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self.0.set_bit(9, value);
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self
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}
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pub fn isolate(&self) -> bool {
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self.0.get_bit(10)
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}
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pub fn set_isolate(mut self, value: bool) -> Self {
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self.0.set_bit(10, value);
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self
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}
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pub fn power_down(&self) -> bool {
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self.0.get_bit(11)
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}
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pub fn set_power_down(mut self, value: bool) -> Self {
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self.0.set_bit(11, value);
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self
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}
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pub fn autoneg_enable(&self) -> bool {
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self.0.get_bit(12)
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}
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pub fn set_autoneg_enable(mut self, value: bool) -> Self {
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self.0.set_bit(12, value);
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self
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}
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pub fn speed0(&self) -> bool {
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self.0.get_bit(13)
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}
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pub fn set_speed0(mut self, value: bool) -> Self {
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self.0.set_bit(13, value);
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self
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}
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pub fn loopback(&self) -> bool {
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self.0.get_bit(14)
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}
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pub fn set_loopback(mut self, value: bool) -> Self {
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self.0.set_bit(14, value);
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self
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}
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pub fn reset(&self) -> bool {
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self.0.get_bit(15)
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}
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pub fn set_reset(mut self, value: bool) -> Self {
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self.0.set_bit(15, value);
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self
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}
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}
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impl PhyRegister for Control {
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fn addr() -> u8 {
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0
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}
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}
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impl From<u16> for Control {
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fn from(value: u16) -> Self {
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Control(value)
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}
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}
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impl Into<u16> for Control {
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fn into(self) -> u16 {
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self.0
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}
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}
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