forked from M-Labs/zynq-rs
77 lines
1.4 KiB
Rust
77 lines
1.4 KiB
Rust
/// The classic no-op
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#[inline]
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pub fn nop() {
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unsafe { llvm_asm!("nop" :::: "volatile") }
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}
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/// Wait For Event
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#[inline]
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pub fn wfe() {
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unsafe { llvm_asm!("wfe" :::: "volatile") }
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}
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/// Send Event
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#[inline]
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pub fn sev() {
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unsafe { llvm_asm!("sev" :::: "volatile") }
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}
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/// Data Memory Barrier
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#[inline]
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pub fn dmb() {
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unsafe { llvm_asm!("dmb" :::: "volatile") }
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}
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/// Data Synchronization Barrier
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#[inline]
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pub fn dsb() {
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unsafe { llvm_asm!("dsb" :::: "volatile") }
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}
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/// Instruction Synchronization Barrier
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#[inline]
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pub fn isb() {
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unsafe { llvm_asm!("isb" :::: "volatile") }
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}
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/// Enable IRQ
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#[inline]
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pub unsafe fn enable_irq() {
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llvm_asm!("cpsie i":::: "volatile");
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}
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/// Disable IRQ, return if IRQ was originally enabled.
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#[inline]
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pub unsafe fn enter_critical() -> bool {
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let mut cpsr: u32;
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llvm_asm!(
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"mrs $0, cpsr
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cpsid i"
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: "=r"(cpsr) ::: "volatile");
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(cpsr & (1 << 7)) == 0
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}
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#[inline]
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pub unsafe fn exit_critical(enable: bool) {
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// https://stackoverflow.com/questions/40019929/temporarily-disable-interrupts-on-arm
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let mask: u32 = if enable {
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1 << 7
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} else {
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0
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};
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llvm_asm!(
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"mrs r1, cpsr
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bic r1, r1, $0
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msr cpsr_c, r1"
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:: "r"(mask) : "r1");
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}
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/// Exiting IRQ
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#[inline]
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pub unsafe fn exit_irq() {
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llvm_asm!("
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mrs r0, SPSR
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msr CPSR, r0
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" ::: "r0");
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}
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