forked from M-Labs/zynq-rs
330 lines
9.5 KiB
Rust
330 lines
9.5 KiB
Rust
///! Register definitions for System Level Control
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use volatile_register::{RO, WO, RW};
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use crate::{register, register_bit, register_bits, register_at, regs::RegisterW, regs::RegisterRW};
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pub enum PllSource {
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IoPll = 0b00,
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ArmPll = 0b10,
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DdrPll = 0b11,
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}
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#[repr(C)]
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pub struct RegisterBlock {
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pub scl: RW<u32>,
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pub slcr_lock: SlcrLock,
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pub slcr_unlock: SlcrUnlock,
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pub slcr_locksta: RO<u32>,
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reserved0: [u32; 60],
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pub arm_pll_ctrl: RW<u32>,
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pub ddr_pll_ctrl: RW<u32>,
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pub io_pll_ctrl: RW<u32>,
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pub pll_status: RO<u32>,
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pub arm_pll_cfg: RW<u32>,
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pub ddr_pll_cfg: RW<u32>,
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pub io_pll_cfg: RW<u32>,
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reserved1: [u32; 1],
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pub arm_clk_ctrl: RW<u32>,
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pub ddr_clk_ctrl: RW<u32>,
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pub dci_clk_ctrl: RW<u32>,
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pub aper_clk_ctrl: AperClkCtrl,
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pub usb0_clk_ctrl: RW<u32>,
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pub usb1_clk_ctrl: RW<u32>,
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pub gem0_rclk_ctrl: RW<u32>,
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pub gem1_rclk_ctrl: RW<u32>,
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pub gem0_clk_ctrl: RW<u32>,
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pub gem1_clk_ctrl: RW<u32>,
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pub smc_clk_ctrl: RW<u32>,
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pub lqspi_clk_ctrl: RW<u32>,
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pub sdio_clk_ctrl: RW<u32>,
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pub uart_clk_ctrl: UartClkCtrl,
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pub spi_clk_ctrl: RW<u32>,
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pub can_clk_ctrl: RW<u32>,
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pub can_mioclk_ctrl: RW<u32>,
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pub dbg_clk_ctrl: RW<u32>,
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pub pcap_clk_ctrl: RW<u32>,
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pub topsw_clk_ctrl: RW<u32>,
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pub fpga0_clk_ctrl: RW<u32>,
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pub fpga0_thr_ctrl: RW<u32>,
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pub fpga0_thr_cnt: RW<u32>,
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pub fpga0_thr_sta: RO<u32>,
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pub fpga1_clk_ctrl: RW<u32>,
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pub fpga1_thr_ctrl: RW<u32>,
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pub fpga1_thr_cnt: RW<u32>,
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pub fpga1_thr_sta: RO<u32>,
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pub fpga2_clk_ctrl: RW<u32>,
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pub fpga2_thr_ctrl: RW<u32>,
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pub fpga2_thr_cnt: RW<u32>,
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pub fpga2_thr_sta: RO<u32>,
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pub fpga3_clk_ctrl: RW<u32>,
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pub fpga3_thr_ctrl: RW<u32>,
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pub fpga3_thr_cnt: RW<u32>,
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pub fpga3_thr_sta: RO<u32>,
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reserved2: [u32; 5],
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pub clk_621_true: RW<u32>,
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reserved3: [u32; 14],
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pub pss_rst_ctrl: RW<u32>,
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pub ddr_rst_ctrl: RW<u32>,
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pub topsw_rst_ctrl: RW<u32>,
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pub dmac_rst_ctrl: RW<u32>,
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pub usb_rst_ctrl: RW<u32>,
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pub gem_rst_ctrl: RW<u32>,
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pub sdio_rst_ctrl: RW<u32>,
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pub spi_rst_ctrl: RW<u32>,
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pub can_rst_ctrl: RW<u32>,
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pub i2c_rst_ctrl: RW<u32>,
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pub uart_rst_ctrl: UartRstCtrl,
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pub gpio_rst_ctrl: RW<u32>,
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pub lqspi_rst_ctrl: RW<u32>,
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pub smc_rst_ctrl: RW<u32>,
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pub ocm_rst_ctrl: RW<u32>,
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reserved4: [u32; 1],
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pub fpga_rst_ctrl: RW<u32>,
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pub a9_cpu_rst_ctrl: RW<u32>,
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reserved5: [u32; 1],
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pub rs_awdt_ctrl: RW<u32>,
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reserved6: [u32; 2],
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pub reboot_status: RW<u32>,
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pub boot_mode: RW<u32>,
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reserved7: [u32; 40],
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pub apu_ctrl: RW<u32>,
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pub wdt_clk_sel: RW<u32>,
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reserved8: [u32; 78],
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pub tz_dma_ns: RW<u32>,
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pub tz_dma_irq_ns: RW<u32>,
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pub tz_dma_periph_ns: RW<u32>,
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reserved9: [u32; 57],
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pub pss_idcode: RW<u32>,
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reserved10: [u32; 51],
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pub ddr_urgent: RW<u32>,
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reserved11: [u32; 2],
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pub ddr_cal_start: RW<u32>,
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reserved12: [u32; 1],
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pub ddr_ref_start: RW<u32>,
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pub ddr_cmd_sta: RW<u32>,
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pub ddr_urgent_sel: RW<u32>,
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pub ddr_dfi_status: RW<u32>,
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reserved13: [u32; 55],
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pub mio_pin_00: RW<u32>,
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pub mio_pin_01: RW<u32>,
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pub mio_pin_02: RW<u32>,
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pub mio_pin_03: RW<u32>,
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pub mio_pin_04: RW<u32>,
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pub mio_pin_05: RW<u32>,
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pub mio_pin_06: RW<u32>,
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pub mio_pin_07: RW<u32>,
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pub mio_pin_08: RW<u32>,
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pub mio_pin_09: RW<u32>,
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pub mio_pin_10: RW<u32>,
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pub mio_pin_11: RW<u32>,
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pub mio_pin_12: RW<u32>,
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pub mio_pin_13: RW<u32>,
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pub mio_pin_14: RW<u32>,
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pub mio_pin_15: RW<u32>,
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pub mio_pin_16: RW<u32>,
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pub mio_pin_17: RW<u32>,
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pub mio_pin_18: RW<u32>,
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pub mio_pin_19: RW<u32>,
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pub mio_pin_20: RW<u32>,
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pub mio_pin_21: RW<u32>,
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pub mio_pin_22: RW<u32>,
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pub mio_pin_23: RW<u32>,
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pub mio_pin_24: RW<u32>,
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pub mio_pin_25: RW<u32>,
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pub mio_pin_26: RW<u32>,
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pub mio_pin_27: RW<u32>,
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pub mio_pin_28: RW<u32>,
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pub mio_pin_29: RW<u32>,
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pub mio_pin_30: RW<u32>,
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pub mio_pin_31: RW<u32>,
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pub mio_pin_32: RW<u32>,
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pub mio_pin_33: RW<u32>,
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pub mio_pin_34: RW<u32>,
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pub mio_pin_35: RW<u32>,
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pub mio_pin_36: RW<u32>,
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pub mio_pin_37: RW<u32>,
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pub mio_pin_38: RW<u32>,
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pub mio_pin_39: RW<u32>,
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pub mio_pin_40: RW<u32>,
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pub mio_pin_41: RW<u32>,
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pub mio_pin_42: RW<u32>,
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pub mio_pin_43: RW<u32>,
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pub mio_pin_44: RW<u32>,
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pub mio_pin_45: RW<u32>,
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pub mio_pin_46: RW<u32>,
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pub mio_pin_47: RW<u32>,
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pub mio_pin_48: MioPin48,
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pub mio_pin_49: MioPin49,
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pub mio_pin_50: RW<u32>,
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pub mio_pin_51: RW<u32>,
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pub mio_pin_52: RW<u32>,
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pub mio_pin_53: RW<u32>,
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reserved14: [u32; 11],
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pub mio_loopback: RW<u32>,
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reserved15: [u32; 1],
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pub mio_mst_tri0: RW<u32>,
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pub mio_mst_tri1: RW<u32>,
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reserved16: [u32; 7],
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pub sd0_wp_cd_sel: RW<u32>,
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pub sd1_wp_cd_sel: RW<u32>,
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reserved17: [u32; 50],
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pub lvl_shftr_en: RW<u32>,
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reserved18: [u32; 3],
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pub ocm_cfg: RW<u32>,
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reserved19: [u32; 123],
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pub gpiob_ctrl: RW<u32>,
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pub gpiob_cfg_cmos18: RW<u32>,
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pub gpiob_cfg_cmos25: RW<u32>,
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pub gpiob_cfg_cmos33: RW<u32>,
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reserved20: [u32; 1],
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pub gpiob_cfg_hstl: RW<u32>,
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pub gpiob_drvr_bias_ctrl: RW<u32>,
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reserved21: [u32; 9],
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pub ddriob_addr1: RW<u32>,
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pub ddriob_data0: RW<u32>,
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pub ddriob_data1: RW<u32>,
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pub ddriob_diff0: RW<u32>,
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pub ddriob_diff1: RW<u32>,
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pub ddriob_clock: RW<u32>,
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pub w_addr: RW<u32>,
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pub w_data: RW<u32>,
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pub w_diff: RW<u32>,
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pub w_clock: RW<u32>,
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pub ddriob_ddr_ctrl: RW<u32>,
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pub ddriob_dci_ctrl: RW<u32>,
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pub ddriob_dci_status: RW<u32>,
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}
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register_at!(RegisterBlock, 0xF8000000, new);
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impl RegisterBlock {
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pub fn unlocked<F: FnMut(&mut Self) -> R, R>(mut f: F) -> R {
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let mut self_ = Self::new();
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self_.slcr_unlock.unlock();
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let r = f(&mut self_);
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self_.slcr_lock.lock();
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r
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}
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}
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register!(slcr_lock, SlcrLock, WO, u32);
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register_bits!(slcr_lock, lock_key, u16, 0, 15);
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impl SlcrLock {
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pub fn lock(&mut self) {
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self.write(
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Self::zeroed()
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.lock_key(0x767B)
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);
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}
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}
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register!(slcr_unlock, SlcrUnlock, WO, u32);
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register_bits!(slcr_unlock, unlock_key, u16, 0, 15);
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impl SlcrUnlock {
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pub fn unlock(&mut self) {
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self.write(
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Self::zeroed()
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.unlock_key(0xDF0D)
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);
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}
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}
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register!(aper_clk_ctrl, AperClkCtrl, RW, u32);
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register_bit!(aper_clk_ctrl, uart1_cpu_1xclkact, 21);
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register_bit!(aper_clk_ctrl, uart0_cpu_1xclkact, 20);
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impl AperClkCtrl {
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pub fn enable_uart0(&mut self) {
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self.modify(|_, w| w.uart0_cpu_1xclkact(true));
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}
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pub fn enable_uart1(&mut self) {
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self.modify(|_, w| w.uart1_cpu_1xclkact(true));
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}
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}
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register!(uart_clk_ctrl, UartClkCtrl, RW, u32);
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register_bit!(uart_clk_ctrl, clkact0, 0);
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register_bit!(uart_clk_ctrl, clkact1, 1);
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register_bits!(uart_clk_ctrl, divisor, u8, 8, 13);
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register_bits!(uart_clk_ctrl, srcsel, u8, 4, 5);
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register_at!(UartClkCtrl, 0xF8000154, new);
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impl UartClkCtrl {
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pub fn enable_uart0(&mut self) {
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self.modify(|_, w| {
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// a. Clock divisor, slcr.UART_CLK_CTRL[DIVISOR] = 0x14.
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// b. Select the IO PLL, slcr.UART_CLK_CTRL[SRCSEL] = 0.
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// c. Enable the UART 0 Reference clock, slcr.UART_CLK_CTRL [CLKACT0] = 1.
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w.divisor(0x14)
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.srcsel(PllSource::IoPll as u8)
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.clkact0(true)
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})
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}
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pub fn enable_uart1(&mut self) {
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self.modify(|_, w| {
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// a. Clock divisor, slcr.UART_CLK_CTRL[DIVISOR] = 0x14.
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// b. Select the IO PLL, slcr.UART_CLK_CTRL[SRCSEL] = 0.
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// c. Enable the UART 1 Reference clock, slcr.UART_CLK_CTRL [CLKACT1] = 1.
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w.divisor(0x14)
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.srcsel(PllSource::IoPll as u8)
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.clkact1(true)
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})
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}
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}
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register!(uart_rst_ctrl, UartRstCtrl, RW, u32);
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register_bit!(uart_rst_ctrl, uart0_ref_rst, 3);
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register_bit!(uart_rst_ctrl, uart1_ref_rst, 2);
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register_bit!(uart_rst_ctrl, uart0_cpu1x_rst, 1);
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register_bit!(uart_rst_ctrl, uart1_cpu1x_rst, 0);
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register_at!(UartRstCtrl, 0xF8000228, new);
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impl UartRstCtrl {
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pub fn reset_uart0(&mut self) {
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self.modify(|_, w|
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w.uart0_ref_rst(true)
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.uart0_cpu1x_rst(true)
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);
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self.modify(|_, w|
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w.uart0_ref_rst(false)
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.uart0_cpu1x_rst(false)
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);
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}
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pub fn reset_uart1(&mut self) {
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self.modify(|_, w|
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w.uart1_ref_rst(true)
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.uart1_cpu1x_rst(true)
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);
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self.modify(|_, w|
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w.uart1_ref_rst(false)
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.uart1_cpu1x_rst(false)
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);
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}
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}
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/// Used for MioPin*.io_type
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pub enum IoBufferType {
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Lvcmos18 = 0b001,
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Lvcmos25 = 0b010,
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Lvcmos33 = 0b011,
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Hstl = 0b100,
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}
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macro_rules! mio_pin_register {
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($mod_name: ident, $struct_name: ident) => (
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register!($mod_name, $struct_name, RW, u32);
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register_bit!($mod_name, disable_rcvr, 13);
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register_bit!($mod_name, pullup, 12);
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register_bits!($mod_name, io_type, u8, 9, 11);
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register_bit!($mod_name, speed, 8);
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register_bits!($mod_name, l3_sel, u8, 5, 7);
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register_bits!($mod_name, l2_sel, u8, 3, 4);
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register_bit!($mod_name, l1_sel, 2);
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register_bit!($mod_name, l0_sel, 1);
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register_bit!($mod_name, tri_enable, 0);
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);
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}
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mio_pin_register!(mio_pin_48, MioPin48);
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mio_pin_register!(mio_pin_49, MioPin49);
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