9 Commits (1804c4c6e87092116156eb1abb711f2d92e6aaa5)

Author	SHA1	Message	Date
Björn Stein	1804c4c6e8	cortex_a9: add proper L1 cache invalidation	2019-10-18 00:11:51 +02:00
Astro	1f9ad5ff62	delint	2019-08-11 00:56:54 +02:00
Astro	9bebfb49bc	begin MMU implementation	2019-06-17 03:32:10 +02:00
Astro	69b65b5f72	cortex_a9 regs: allow defining bit fields	2019-06-17 01:36:11 +02:00
Astro	1e16beb707	cortex_a9::regs: use crate::regs interface	2019-06-12 00:20:23 +02:00
Astro	6d15b82a3e	cortex_a9::regs: init U bit for unaligned access	2019-06-04 23:47:23 +02:00
Astro	75bb755327	extend linker script	2019-05-27 22:38:10 +02:00
Astro	1033648c3e	add l1_cache_init()	2019-05-23 19:05:06 +02:00
Astro	9b414e2408	PoC: boot, uart output in qemu	2019-05-05 14:56:23 +02:00