forked from M-Labs/zynq-rs
enable_uart0(): add srcsel
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55957eea09
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fdc6c38de6
15
src/slcr.rs
15
src/slcr.rs
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@ -2,10 +2,17 @@ use volatile_register::{RO, WO, RW};
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use crate::{register, register_bit, register_bits, regs::Register};
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pub enum PllSource {
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IoPll = 0b00,
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ArmPll = 0b10,
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DdrPll = 0b11,
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}
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register!(uart_clk_ctrl, UartClkCtrl, u32);
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register_bit!(uart_clk_ctrl, clkact0, 0);
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register_bit!(uart_clk_ctrl, clkact1, 1);
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register_bits!(uart_clk_ctrl, divisor, u8, 8, 13);
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register_bits!(uart_clk_ctrl, srcsel, u8, 4, 5);
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impl UartClkCtrl {
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const ADDR: *mut Self = 0xF8000154 as *mut _;
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@ -15,8 +22,12 @@ impl UartClkCtrl {
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pub fn enable_uart0(&self) {
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self.modify(|_, w| {
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w.clkact0(true)
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.divisor(0x14)
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// a. Clock divisor, slcr.UART_CLK_CTRL[DIVISOR] = 0x14.
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// b. Select the IO PLL, slcr.UART_CLK_CTRL[SRCSEL] = 0.
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// c. Enable the UART 0 Reference clock, slcr.UART_CLK_CTRL [CLKACT0] = 1.
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w.divisor(0x14)
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.srcsel(PllSource::IoPll as u8)
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.clkact0(true)
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})
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}
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}
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@ -11,10 +11,6 @@ impl Uart {
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uart_rst_ctrl.reset_uart0();
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// TODO: Route UART 0 RxD/TxD Signals to MIO Pins
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// a. Clock divisor, slcr.UART_CLK_CTRL[DIVISOR] = 0x14.
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// b. Select the IO PLL, slcr.UART_CLK_CTRL[SRCSEL] = 0.
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// c. Enable the UART 0 Reference clock, slcr.UART_CLK_CTRL [CLKACT0] = 1.
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// d. Disable UART 1 Reference clock, slcr.UART_CLK_CTRL [CLKACT1] bit = 0.
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let uart_clk_ctrl = super::slcr::UartClkCtrl::new();
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uart_clk_ctrl.enable_uart0();
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