forked from M-Labs/zynq-rs
slcr: add soft_rst()
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parent
b961526b97
commit
ee7ae7f7cc
15
src/slcr.rs
15
src/slcr.rs
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@ -66,7 +66,7 @@ pub struct RegisterBlock {
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reserved2: [u32; 5],
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reserved2: [u32; 5],
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pub clk_621_true: RW<u32>,
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pub clk_621_true: RW<u32>,
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reserved3: [u32; 14],
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reserved3: [u32; 14],
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pub pss_rst_ctrl: RW<u32>,
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pub pss_rst_ctrl: PssRstCtrl,
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pub ddr_rst_ctrl: RW<u32>,
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pub ddr_rst_ctrl: RW<u32>,
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pub topsw_rst_ctrl: RW<u32>,
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pub topsw_rst_ctrl: RW<u32>,
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pub dmac_rst_ctrl: RW<u32>,
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pub dmac_rst_ctrl: RW<u32>,
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@ -207,6 +207,16 @@ impl RegisterBlock {
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self_.slcr_lock.lock();
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self_.slcr_lock.lock();
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r
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r
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}
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}
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/// Perform a soft reset
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pub fn soft_reset(&mut self) -> ! {
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self.pss_rst_ctrl.write(
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PssRstCtrl::zeroed()
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.soft_rst(true)
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);
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unreachable!()
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}
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}
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}
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register!(slcr_lock, SlcrLock, WO, u32);
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register!(slcr_lock, SlcrLock, WO, u32);
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@ -305,6 +315,9 @@ impl UartRstCtrl {
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}
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}
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}
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}
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register!(pss_rst_ctrl, PssRstCtrl, RW, u32);
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register_bit!(pss_rst_ctrl, soft_rst, 1);
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/// Used for MioPin*.io_type
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/// Used for MioPin*.io_type
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#[repr(u8)]
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#[repr(u8)]
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pub enum IoBufferType {
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pub enum IoBufferType {
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