mmu: switch bufferable=1 (writeback) for DDR pages

2020-06-14 23:49:17 +02:00 · 2020-06-14 23:49:17 +02:00 · aebce435e2
commit aebce435e2
parent 98f5099684
1 changed files with 1 additions and 1 deletions
--- a/libcortex_a9/src/mmu.rs
+++ b/libcortex_a9/src/mmu.rs
@ -132,7 +132,7 @@ impl L1Table {
                domain: 0b1111,
                exec: true,
                cacheable: true,
-                bufferable: false,
+                bufferable: true,
            });
        }
        /* 0x40000000 - 0x7fffffff (FPGA slave0) */