forked from M-Labs/zynq-rs
reduce ethernet verbosity
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@ -2,7 +2,7 @@ use core::{
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marker::PhantomData,
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ops::{Deref, DerefMut},
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};
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use log::{error, info, warn};
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use log::{debug, info, warn, error};
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use libregister::*;
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use super::slcr;
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use super::clocks::Clocks;
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@ -132,7 +132,7 @@ fn calculate_tx_divisors(tx_clock: u32) -> (u8, u8) {
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}
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}
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let result = best.unwrap();
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info!("Eth TX clock for {}: {} / {} / {} = {}",
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debug!("Eth TX clock for {}: {} / {} / {} = {}",
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tx_clock, io_pll,
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result.0, result.1,
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io_pll / result.0 as u32 / result.1 as u32
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