forked from M-Labs/zynq-rs
added registers for device configuration interface (devc)
This commit is contained in:
Stewart Mackenzie
parent
01e9f2031a
commit
a23506fb8a
29
libboard_zynq/src/devc/mod.rs
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29
libboard_zynq/src/devc/mod.rs
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@ -0,0 +1,29 @@
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use core::fmt;
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use libregister::*;
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mod regs;
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pub struct DevC {
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regs: &'static mut regs::RegisterBlock,
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}
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impl DevC {
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pub fn new() -> Self {
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DevC {
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regs: regs::RegisterBlock::devc(),
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}
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}
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pub fn enable(&mut self) {
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self.regs.control.modify(|_, w| {
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w.pcap_mode(true)
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.pcap_pr(true)
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})
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}
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pub fn disable(&mut self) {
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self.regs.control.modify(|_, w| {
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w.pcap_mode(false)
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.pcap_pr(false)
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})
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}
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}
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213
libboard_zynq/src/devc/regs.rs
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213
libboard_zynq/src/devc/regs.rs
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@ -0,0 +1,213 @@
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use volatile_register::{RO, WO, RW};
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use libregister::{
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register, register_at,
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register_bit, register_bits, register_bits_typed,
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};
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#[repr(C)]
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pub struct RegisterBlock {
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pub control: Control,
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pub cfg: Cfg,
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pub lock: Lock,
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pub int_sts: IntSts,
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pub int_mask: IntMask,
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pub status: Status,
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pub dma_src_addr: DmaSrcAddr,
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pub dma_dest_addr: DmaDestAddr,
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pub dma_src_len: DmaSrcLen,
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pub dma_dest_len: DmaDestLen,
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pub multiboot_addr: MultibootAddr,
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pub unlock: Unlock,
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pub mctrl: MCtrl,
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pub xadcif_cfg: XADCIfCfg,
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pub xadcif_int_sts: XADCIfIntSts,
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pub xadcif_int_mask: XADCIfIntMask,
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pub xadcif_msts: XADCIf_Msts,
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pub xadcif_cmdfifo: XADCIf_CmdFIFO,
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pub xadcif_rdfifo: XADCIf_RdFIFO,
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pub xadcif_mctl: XADCIf_MCtl,
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}
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register_at!(RegisterBlock, 0xF8007000, devc);
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register!(control, Control, RW, u32);
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register_bit!(control, force_rst, 31);
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register_bit!(control, pcfg_prog_b, 30);
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register_bit!(control, pcfg_pro_cnt_4k, 29);
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register_bit!(control, pcap_pr, 27);
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register_bit!(control, pcap_mode, 26);
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register_bit!(control, pcap_rate_en, 25);
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register_bit!(control, multiboot_en, 24);
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register_bit!(control, jtag_chain_dis, 23);
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register_bit!(control, pcfg_aes_fuse, 12);
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register_bits!(control, pcfg_aes_en, u8, 9, 11);
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register_bit!(control, seu_en, 8);
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register_bit!(control, sec_en, 7);
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register_bit!(control, spniden, 6);
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register_bit!(control, spiden, 5);
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register_bit!(control, niden, 4);
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register_bit!(control, dbgen, 3);
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register_bits!(control, dap_en, u8, 0, 2);
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register!(lock, Lock, RW, u32);
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register_bit!(lock, aes_fuse_lock, 4);
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register_bit!(lock, aes_en, 3);
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register_bit!(lock, seu, 2);
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register_bit!(lock, sec, 1);
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register_bit!(lock, dbg, 0);
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register!(cfg, Cfg, RW, u32);
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#[allow(unused)]
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#[repr(u8)]
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pub enum RFifoTh {
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OneFourthFull = 0b00, // One fourth full for read
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HalfFull = 0b01, // Half full for read
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ThreeFourthFull = 0b10, // Three fourth full for read
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Full = 0b11, // Full for read
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}
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register_bits_typed!(cfg, rfifo_th, u8, RFifoTh, 10, 11);
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#[allow(unused)]
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#[repr(u8)]
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pub enum WFifoTh {
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OneFourthEmpty = 0b00, // One fourth empty for write
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HalfEmpty = 0b01, // Half empty for write
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ThreeFourthEmpty = 0b10, // Three fourth empty for write
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Empty = 0b11, // Empty for write
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}
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register_bits_typed!(cfg, wfifo_th, u8, WFifoTh, 10, 11);
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register_bit!(cfg, rclk_edge, 7);
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register_bit!(cfg, wclk_edge, 6);
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register_bit!(cfg, disable_src_inc, 5);
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register_bit!(cfg, disable_dst_inc, 4);
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register!(int_sts, IntSts, RW, u32);
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register_bit!(int_sts, pps_gts_usr_b_int, 31);
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register_bit!(int_sts, pps_fst_cfg_b_int, 30);
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register_bit!(int_sts, pps_gpwrdwn_b_int, 29);
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register_bit!(int_sts, pps_gts_cfg_b_int, 27);
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register_bit!(int_sts, pps_cfg_reset_b_int, 26);
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register_bit!(int_sts, ixr_axi_wto, 23);
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register_bit!(int_sts, ixr_axi_werr, 22);
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register_bit!(int_sts, ixr_axi_rto, 21);
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register_bit!(int_sts, ixr_axi_rerr, 20);
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register_bit!(int_sts, ixr_rx_fifo_ov, 18);
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register_bit!(int_sts, ixr_wr_fifo_lvl, 17);
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register_bit!(int_sts, ixr_rd_fifo_lvl, 16);
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register_bit!(int_sts, ixr_dma_cmd_err, 15);
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register_bit!(int_sts, ixr_dma_q_ov, 14);
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register_bit!(int_sts, ixr_dma_done, 13);
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register_bit!(int_sts, ixr_d_p_done, 12);
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register_bit!(int_sts, ixr_p2d_len_err, 11);
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register_bit!(int_sts, ixr_pcfg_hmac_err, 6);
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register_bit!(int_sts, ixr_pcfg_seu_err, 5);
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register_bit!(int_sts, ixr_pcfg_por_b, 4);
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register_bit!(int_sts, ixr_pcfg_cfg_rst, 3);
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register_bit!(int_sts, ixr_pcfg_done, 2);
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register_bit!(int_sts, ixr_pcfg_init_pe, 1);
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register_bit!(int_sts, ixr_pcfg_init_ne, 0);
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register!(int_mask, IntMask, RW, u32);
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register_bit!(int_mask, m_pss_gts_usr_b_int, 31);
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register_bit!(int_mask, m_pss_fst_cfg_b_int, 30);
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register_bit!(int_mask, m_pss_gpwrdwn_b_int, 29);
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register_bit!(int_mask, m_pss_gts_cfg_b_int, 28);
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register_bit!(int_mask, m_pss_cfg_reset_b_int, 27);
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register_bit!(int_mask, ixr_axi_wto, 23);
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register_bit!(int_mask, ixr_axi_werr, 22);
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register_bit!(int_mask, ixr_axi_rto, 21);
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register_bit!(int_mask, ixr_axi_rerr, 20);
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register_bit!(int_mask, ixr_rx_fifo_ov, 18);
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register_bit!(int_mask, ixr_wr_fifo_lvl, 17);
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register_bit!(int_mask, ixr_rd_fifo_lvl, 16);
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register_bit!(int_mask, ixr_dma_cmd_err, 15);
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register_bit!(int_mask, ixr_dma_q_ov, 14);
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register_bit!(int_mask, ixr_dma_done, 13);
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register_bit!(int_mask, ixr_d_p_done, 12);
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register_bit!(int_mask, ixr_p2d_len_err, 11);
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register_bit!(int_mask, ixr_pcfg_hmac_err, 6);
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register_bit!(int_mask, ixr_pcfg_seu_err, 5);
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register_bit!(int_mask, ixr_pcfg_por_b, 4);
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register_bit!(int_mask, ixr_pcfg_cfg_rst, 3);
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register_bit!(int_mask, ixr_pcfg_done, 2);
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register_bit!(int_mask, ixr_pcfg_init_pe, 1);
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register_bit!(int_mask, ixr_pcfg_init_ne, 0);
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register!(status, Status, RO, u32);
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register_bit!(status, dma_cmd_q_f, 31);
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register_bit!(status, dma_cmd_q_e, 30);
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register_bits!(status, dma_done_cnt, u8, 28, 29);
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register_bits!(status, rx_fifo_lvl, u8, 20, 24);
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register_bits!(status, tx_fifo_lvl, u8, 12, 18);
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register_bit!(status, pss_gts_usr_b, 11);
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register_bit!(status, pss_fst_cfg_b, 10);
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register_bit!(status, pss_gpwrdwn_b, 9);
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register_bit!(status, pss_gts_cfg_b, 8);
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register_bit!(status, secure_rst, 7);
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register_bit!(status, illegal_apb_access , 6);
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register_bit!(status, pss_cfg_reset_b, 5);
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register_bit!(status, pcfg_init, 4);
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register_bit!(status, efuse_sw_reserve, 3);
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register_bit!(status, efuse_sec_en, 2);
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register_bit!(status, efuse_jtag_dis, 1);
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register!(dma_src_addr, DmaSrcAddr, RW, u32);
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register_bits!(dma_src_addr, src_addr, u8, 0, 31);
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register!(dma_dest_addr, DmaDestAddr, RW, u32);
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register_bits!(dma_dest_addr, dest_addr, u8, 0, 31);
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register!(dma_src_len, DmaSrcLen, RW, u32);
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register_bits!(dma_src_len, dma_len, u8, 0, 26);
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register!(dma_dest_len, DmaDestLen, RW, u32);
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register_bits!(dma_dest_len, dma_len, u8, 0, 26);
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register!(multiboot_addr, MultibootAddr, RW, u32);
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register_bits!(multiboot_addr, multiboot_addr, u8, 0, 12);
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register!(unlock, Unlock, RW, u32);
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register_bits!(unlock, unlock, u8, 0, 31);
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register!(mctrl, MCtrl, RW, u32);
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register_bits!(mctrl, ps_version, u8, 28, 31);
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register_bit!(mctrl, pcfg_por_b, 8);
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register_bit!(mctrl, pcap_lpbk, 4);
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register!(xadcif_cfg, XADCIfCfg, RW, u32);
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register_bit!(xadcif_cfg, enable, 31);
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register_bits!(xadcif_cfg, cfifoth, u8, 20, 23);
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register_bits!(xadcif_cfg, dfifoth, u8, 16, 19);
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register_bit!(xadcif_cfg, wedge, 13);
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register_bit!(xadcif_cfg, redge, 13);
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register_bits!(xadcif_cfg, tckrate, u8, 8, 9);
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register_bits!(xadcif_cfg, igap, u8, 0, 4);
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register!(xadcif_int_sts, XADCIfIntSts, RW, u32);
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register_bit!(xadcif_int_sts, cfifo_lth, 9);
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register_bit!(xadcif_int_sts, dfifo_gth, 8);
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register_bit!(xadcif_int_sts, ot, 7);
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register_bits!(xadcif_int_sts, alm, u8, 0, 6);
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register!(xadcif_int_mask, XADCIfIntMask, RW, u32);
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register_bit!(xadcif_int_mask, m_cfifo_lth, 9);
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register_bit!(xadcif_int_mask, m_dfifo_gth, 8);
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register_bit!(xadcif_int_mask, m_ot, 7);
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register_bits!(xadcif_int_mask, m_alm, u8, 0, 6);
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register!(xadcif_msts, XADCIf_Msts, RO, u32);
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register_bits!(xadcif_msts, cfifo_lvl, u8, 16, 19);
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register_bits!(xadcif_msts, dfifo_lvl, u8, 12, 15);
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register_bit!(xadcif_msts, cfifof, 11);
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register_bit!(xadcif_msts, cfifoe, 10);
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register_bit!(xadcif_msts, dfifof, 9);
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register_bit!(xadcif_msts, dfifoe, 8);
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register_bit!(xadcif_msts, ot, 7);
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register_bits!(xadcif_msts, alm, u8, 0, 6);
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register!(xadcif_cmdfifo, XADCIf_CmdFIFO, WO, u32);
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register_bits!(xadcif_cmdfifo, cmd, u8, 0, 31);
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register!(xadcif_rdfifo, XADCIf_RdFIFO, RO, u32);
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register_bits!(xadcif_rdfifo, rddata, u8, 0, 31);
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register!(xadcif_mctl, XADCIf_MCtl, RW, u32);
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register_bit!(xadcif_mctl, reset, 4);
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@ -3,6 +3,7 @@
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pub mod slcr;
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pub mod slcr;
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pub mod clocks;
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pub mod clocks;
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pub mod uart;
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pub mod uart;
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pub mod devc;
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pub mod stdio;
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pub mod stdio;
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pub mod eth;
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pub mod eth;
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pub mod axi_hp;
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pub mod axi_hp;
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