forked from M-Labs/zynq-rs
uart: move logic outside regs
This commit is contained in:
parent
275f297309
commit
7872e00182
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@ -123,7 +123,7 @@ macro_rules! register {
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macro_rules! register_bit {
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($mod_name: ident, $name: ident, $bit: expr) => (
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impl $mod_name::Read {
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fn $name(&self) -> bool {
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pub fn $name(&self) -> bool {
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use bit_field::BitField;
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self.inner.get_bit($bit)
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@ -131,7 +131,7 @@ macro_rules! register_bit {
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}
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impl $mod_name::Write {
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fn $name(mut self, value: bool) -> Self {
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pub fn $name(mut self, value: bool) -> Self {
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use bit_field::BitField;
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self.inner.set_bit($bit, value);
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@ -146,7 +146,7 @@ macro_rules! register_bit {
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macro_rules! register_bits {
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($mod_name: ident, $name: ident, $type: ty, $bit_begin: expr, $bit_end: expr) => (
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impl $mod_name::Read {
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fn $name(&self) -> $type {
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pub fn $name(&self) -> $type {
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use bit_field::BitField;
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self.inner.get_bits($bit_begin..=$bit_end) as $type
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@ -154,7 +154,7 @@ macro_rules! register_bits {
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}
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impl $mod_name::Write {
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fn $name(mut self, value: $type) -> Self {
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pub fn $name(mut self, value: $type) -> Self {
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use bit_field::BitField;
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self.inner.set_bits($bit_begin..=$bit_end, value.into());
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102
src/uart/mod.rs
102
src/uart/mod.rs
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@ -2,11 +2,20 @@
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use core::fmt;
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use crate::regs::*;
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mod regs;
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pub use regs::RegisterBlock;
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#[repr(u8)]
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pub enum ParityMode {
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EvenParity = 0b000,
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OddParity = 0b001,
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ForceTo0 = 0b010,
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ForceTo1 = 0b011,
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}
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pub struct Uart {
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regs: &'static mut RegisterBlock,
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regs: &'static mut regs::RegisterBlock,
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}
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impl Uart {
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@ -18,20 +27,91 @@ impl Uart {
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let uart_clk_ctrl = super::slcr::UartClkCtrl::new();
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uart_clk_ctrl.enable_uart0();
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Uart {
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regs: RegisterBlock::uart0(),
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}.init()
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let self_ = Uart {
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regs: regs::RegisterBlock::uart0(),
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};
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self_.configure();
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self_
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}
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fn init(self) -> Self {
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self.regs.configure();
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self
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pub fn write_byte(&self, value: u8) {
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while self.tx_fifo_full() {}
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self.regs.tx_rx_fifo.write(
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regs::TxRxFifo::zeroed()
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.data(value.into())
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);
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}
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pub fn write_byte(&self, v: u8) {
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while self.regs.tx_fifo_full() {}
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pub fn configure(&self) {
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// Confiugre UART character frame
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// * Disable clock-divider
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// * 8-bit
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// * 1 stop bit
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// * Normal channel mode
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// * no parity
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let parity_mode = ParityMode::ForceTo0;
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self.regs.mode.write(
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regs::Mode::zeroed()
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.par(parity_mode as u8)
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);
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self.regs.write_byte(v);
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// Configure the Baud Rate
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self.disable_rx();
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self.disable_tx();
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// 9,600 baud
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self.regs.baud_rate_gen.write(regs::BaudRateGen::zeroed().cd(651));
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self.regs.baud_rate_divider.write(regs::BaudRateDiv::zeroed().bdiv(7));
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self.reset_rx();
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self.reset_tx();
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self.enable_rx();
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self.enable_tx();
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}
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fn disable_rx(&self) {
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self.regs.control.modify(|_, w| {
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w.rxen(false)
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.rxdis(true)
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})
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}
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fn disable_tx(&self) {
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self.regs.control.modify(|_, w| {
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w.txen(false)
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.txdis(true)
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})
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}
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fn enable_rx(&self) {
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self.regs.control.modify(|_, w| {
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w.rxen(true)
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.rxdis(false)
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})
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}
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fn enable_tx(&self) {
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self.regs.control.modify(|_, w| {
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w.txen(true)
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.txdis(false)
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})
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}
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fn reset_rx(&self) {
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self.regs.control.modify(|_, w| {
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w.rxrst(true)
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})
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}
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fn reset_tx(&self) {
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self.regs.control.modify(|_, w| {
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w.txrst(true)
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})
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}
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pub fn tx_fifo_full(&self) -> bool {
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self.regs.channel_sts.read().txfull()
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}
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}
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116
src/uart/regs.rs
116
src/uart/regs.rs
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@ -2,34 +2,26 @@ use volatile_register::{RO, WO, RW};
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use crate::{register, register_bit, register_bits, regs::*};
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#[repr(u8)]
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pub enum ParityMode {
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EvenParity = 0b000,
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OddParity = 0b001,
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ForceTo0 = 0b010,
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ForceTo1 = 0b011,
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}
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#[repr(C)]
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pub struct RegisterBlock {
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control: Control,
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mode: Mode,
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intrpt_en: RW<u32>,
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intrpt_dis: RW<u32>,
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intrpt_mask: RO<u32>,
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chnl_int_sts: WO<u32>,
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baud_rate_gen: BaudRateGen,
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rcvr_timeout: RW<u32>,
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rcvr_fifo_trigger_level: RW<u32>,
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modem_ctrl: RW<u32>,
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modem_sts: RW<u32>,
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channel_sts: ChannelSts,
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tx_rx_fifo: TxRxFifo,
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baud_rate_divider: BaudRateDiv,
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flow_delay: RW<u32>,
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reserved0: RO<u32>,
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reserved1: RO<u32>,
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tx_fifo_trigger_level: RW<u32>,
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pub control: Control,
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pub mode: Mode,
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pub intrpt_en: RW<u32>,
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pub intrpt_dis: RW<u32>,
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pub intrpt_mask: RO<u32>,
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pub chnl_int_sts: WO<u32>,
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pub baud_rate_gen: BaudRateGen,
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pub rcvr_timeout: RW<u32>,
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pub rcvr_fifo_trigger_level: RW<u32>,
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pub modem_ctrl: RW<u32>,
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pub modem_sts: RW<u32>,
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pub channel_sts: ChannelSts,
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pub tx_rx_fifo: TxRxFifo,
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pub baud_rate_divider: BaudRateDiv,
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pub flow_delay: RW<u32>,
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pub unused0: RO<u32>,
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pub unused1: RO<u32>,
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pub tx_fifo_trigger_level: RW<u32>,
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}
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register!(control, Control, RW, u32);
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@ -66,76 +58,4 @@ impl RegisterBlock {
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pub fn uart1() -> &'static mut Self {
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unsafe { &mut *Self::UART1 }
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}
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pub fn configure(&self) {
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// Confiugre UART character frame
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// * Disable clock-divider
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// * 8-bit
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// * 1 stop bit
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// * Normal channel mode
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// * no parity
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let parity_mode = ParityMode::ForceTo0;
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self.mode.write(Mode::zeroed().par(parity_mode as u8));
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// Configure the Baud Rate
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self.disable_rx();
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self.disable_tx();
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// 9,600 baud
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self.baud_rate_gen.write(BaudRateGen::zeroed().cd(651));
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self.baud_rate_divider.write(BaudRateDiv::zeroed().bdiv(7));
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self.reset_rx();
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self.reset_tx();
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self.enable_rx();
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self.enable_tx();
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}
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pub fn write_byte(&self, value: u8) {
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self.tx_rx_fifo.write(TxRxFifo::zeroed().data(value.into()));
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}
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fn disable_rx(&self) {
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self.control.modify(|_, w| {
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w.rxen(false)
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.rxdis(true)
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})
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}
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fn disable_tx(&self) {
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self.control.modify(|_, w| {
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w.txen(false)
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.txdis(true)
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})
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}
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fn enable_rx(&self) {
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self.control.modify(|_, w| {
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w.rxen(true)
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.rxdis(false)
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})
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}
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fn enable_tx(&self) {
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self.control.modify(|_, w| {
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w.txen(true)
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.txdis(false)
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})
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}
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fn reset_rx(&self) {
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self.control.modify(|_, w| {
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w.rxrst(true)
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})
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}
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fn reset_tx(&self) {
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self.control.modify(|_, w| {
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w.txrst(true)
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})
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}
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pub fn tx_fifo_full(&self) -> bool {
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self.channel_sts.read().txfull()
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}
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}
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