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libcortex_a9: allow access for full 1GB of DDR

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Astro 2020-05-09 01:00:48 +02:00
parent 4e1f46b3e2
commit 66cd0c7630
1 changed files with 1 additions and 14 deletions
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15
libcortex_a9/src/mmu.rs
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@ -123,7 +123,7 @@ impl L1Table {
bufferable: true, bufferable: true,
}); });
/* (DDR cacheable) */ /* (DDR cacheable) */
for ddr in 1..=0x1ff { for ddr in 1..=0x3ff {
self.direct_mapped_section(ddr, L1Section { self.direct_mapped_section(ddr, L1Section {
global: true, global: true,
shareable: true, shareable: true,
@ -135,19 +135,6 @@ impl L1Table {
bufferable: false, bufferable: false,
}); });
} }
/* (unassigned/reserved). */
for undef in 0x1ff..=0x3ff {
self.direct_mapped_section(undef, L1Section {
global: false,
shareable: false,
access: AccessPermissions::PermissionFault,
tex: 0,
domain: 0,
exec: false,
cacheable: false,
bufferable: false,
});
}
/* 0x40000000 - 0x7fffffff (FPGA slave0) */ /* 0x40000000 - 0x7fffffff (FPGA slave0) */
for fpga_slave in 0x400..=0x7ff { for fpga_slave in 0x400..=0x7ff {
self.direct_mapped_section(fpga_slave, L1Section { self.direct_mapped_section(fpga_slave, L1Section {