forked from M-Labs/zynq-rs
parent
4bc1d21ae9
commit
43c3f3e4a6
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@ -12,6 +12,8 @@ pub mod tx;
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pub const MTU: usize = 1536;
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/// Maximum MDC clock
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const MAX_MDC: u32 = 2_500_000;
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/// Clock for GbE
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const TX_1000: u32 = 125_000_000;
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pub struct Eth<RX, TX> {
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regs: &'static mut regs::RegisterBlock,
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@ -152,14 +154,14 @@ impl Eth<(), ()> {
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}
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pub fn gem0(macaddr: [u8; 6]) -> Self {
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Self::setup_gem0_clock(125);
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Self::setup_gem0_clock(TX_1000);
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let regs = regs::RegisterBlock::gem0();
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Self::from_regs(regs, macaddr)
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}
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pub fn gem1(macaddr: [u8; 6]) -> Self {
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Self::setup_gem1_clock(125);
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Self::setup_gem1_clock(TX_1000);
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let regs = regs::RegisterBlock::gem1();
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Self::from_regs(regs, macaddr)
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@ -401,7 +403,7 @@ impl<RX, TX> Eth<RX, TX> {
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.set_restart_autoneg(true)
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);
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// 125 MHz for 1000base-TX
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Self::setup_gem0_clock(125);
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Self::setup_gem0_clock(TX_1000);
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true
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}
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