forked from M-Labs/zynq-rs
finished register definitions
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d9e8a667bd
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244ccdeac2
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@ -2,6 +2,34 @@ use volatile_register::{RO, RW, WO};
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use libregister::{register, register_at, register_bit, register_bits, register_bits_typed};
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#[repr(C)]
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pub struct RegisterBlock {
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pub sdma_system_address: RW<u32>,
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pub block_size_block_count: BlockSizeBlockCount,
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pub argument: RW<u32>,
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pub transfer_mode_command: TransferModeCommand,
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pub responses: [RO<u32>; 4],
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pub buffer: RW<u32>,
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pub present_state: PresentState,
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/// Host. power, block gap, wakeup control
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pub control: Control,
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/// Clock and timeout control, and software reset register.
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pub timing_control: TimingControl,
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pub interrupt_status: InterruptStatus,
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pub interrupt_status_en: InterruptStatusEn,
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pub interrupt_signal_en: InterruptSignalEn,
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pub auto_cmd12_error_status: AutoCmd12ErrorStatus,
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pub capabilities: Capabilities,
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pub max_current_capabilities: MaxCurrentCapabilities,
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pub force_event: ForceEvent,
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pub adma_error_status: AdmaErrorStatus,
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pub adma_system_address: RW<u32>,
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pub boot_data_timeout_counter: RW<u32>,
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pub debug_selection: DebugSelection,
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pub spi_interrupt_support: SpiInterruptSupport,
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pub misc_reg: MiscReg,
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}
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#[allow(unused)]
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#[repr(u8)]
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pub enum CommandType {
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@ -34,7 +62,7 @@ pub enum BusVoltage {
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#[allow(unused)]
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#[repr(u8)]
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pub enum DmaSelect {
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SDMA = 0b00,
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SDMA = 0b00,
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ADMA1 = 0b01,
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ADMA2 = 0b10,
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ADMA3 = 0b11,
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@ -42,7 +70,7 @@ pub enum DmaSelect {
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#[allow(unused)]
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#[repr(u8)]
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/// SDCLK Frequency divisor, d(number) means baseclock divides by (number).
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/// SDCLK Frequency divisor, d(number) means baseclock divided by (number).
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pub enum SdclkFreqDivisor {
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D256 = 0x80,
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D128 = 0x40,
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@ -55,20 +83,19 @@ pub enum SdclkFreqDivisor {
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D1 = 0x00,
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}
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#[repr(C)]
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pub struct RegisterBlock {
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pub sdma_system_address: RO<u32>,
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pub block_size_block_count: BlockSizeBlockCount,
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pub argument: RW<u32>,
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pub transfer_mode_command: TransferModeCommand,
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pub responses: [RO<u32>; 4],
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pub buffer: RW<u32>,
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pub present_state: PresentState,
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/// Host. power, block gap, wakeup control
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pub control: Control,
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/// Clock and timeout control, and software reset register.
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pub timing_control: TimingControl,
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pub interrupt_status: InterruptStatus,
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#[allow(unused)]
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#[repr(u8)]
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pub enum AdmaErrorState {
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StStop = 0b00,
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StFds = 0b01,
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StTfr = 0b11,
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}
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#[allow(unused)]
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#[repr(u8)]
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pub enum SpecificationVersion {
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V1 = 0,
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V2 = 1,
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}
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register_at!(RegisterBlock, 0xE0100000, sd0);
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@ -377,3 +404,144 @@ register_bit!(interrupt_status, dma_interrupt, 3, WTC);
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register_bit!(interrupt_status, block_gap_event, 2, WTC);
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register_bit!(interrupt_status, transfer_complete, 1, WTC);
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register_bit!(interrupt_status, command_complete, 0, WTC);
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register!(interrupt_status_en, InterruptStatusEn, RW, u32);
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register_bit!(interrupt_status_en, ceata_error_status_en, 29);
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register_bit!(interrupt_status_en, target_response_error_status_en, 28);
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register_bit!(interrupt_status_en, adma_error_status_en, 25);
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register_bit!(interrupt_status_en, auto_cmd12_error_status_en, 24);
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register_bit!(interrupt_status_en, current_limit_error_status_en, 23);
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register_bit!(interrupt_status_en, data_end_bit_error_status_en, 22);
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register_bit!(interrupt_status_en, data_crc_error_status_en, 21);
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register_bit!(interrupt_status_en, data_timeout_error_status_en, 20);
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register_bit!(interrupt_status_en, cmd_index_error_status_en, 19);
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register_bit!(interrupt_status_en, cmd_end_bit_error_status_en, 18);
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register_bit!(interrupt_status_en, cmd_crc_error_status_en, 17);
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register_bit!(interrupt_status_en, cmd_timeout_error_status_en, 16);
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register_bit!(interrupt_status_en, fixed_to_0, 15, RO);
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register_bit!(interrupt_status_en, boot_terminate_interrupt_en, 10);
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register_bit!(interrupt_status_en, boot_ack_rcv_en, 9);
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register_bit!(interrupt_status_en, card_interrupt_status_en, 8);
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register_bit!(interrupt_status_en, card_removal_status_en, 7);
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register_bit!(interrupt_status_en, card_insertion_status_en, 6);
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register_bit!(interrupt_status_en, buffer_read_ready_status_en, 5);
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register_bit!(interrupt_status_en, buffer_write_ready_status_en, 4);
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register_bit!(interrupt_status_en, dma_interrupt_status_en, 3);
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register_bit!(interrupt_status_en, block_gap_evt_status_en, 2);
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register_bit!(interrupt_status_en, transfer_complete_status_en, 1);
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register_bit!(interrupt_status_en, cmd_complete_status_en, 0);
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register!(interrupt_signal_en, InterruptSignalEn, RW, u32);
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register_bit!(interrupt_signal_en, ceata_error_signal_en, 29);
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register_bit!(interrupt_signal_en, target_response_error_signal_en, 28);
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register_bit!(interrupt_signal_en, adma_error_signal_en, 25);
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register_bit!(interrupt_signal_en, auto_cmd12_error_signal_en, 24);
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register_bit!(interrupt_signal_en, current_limit_error_signal_en, 23);
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register_bit!(interrupt_signal_en, data_end_bit_error_signal_en, 22);
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register_bit!(interrupt_signal_en, data_crc_error_signal_en, 21);
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register_bit!(interrupt_signal_en, data_timeout_error_signal_en, 20);
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register_bit!(interrupt_signal_en, cmd_index_error_signal_en, 19);
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register_bit!(interrupt_signal_en, cmd_end_bit_error_signal_en, 18);
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register_bit!(interrupt_signal_en, cmd_crc_error_signal_en, 17);
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register_bit!(interrupt_signal_en, cmd_timeout_error_signal_en, 16);
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register_bit!(interrupt_signal_en, fixed_to_0, 15, RO);
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register_bit!(interrupt_signal_en, boot_terminate_interrupt_signal_en, 10);
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register_bit!(interrupt_signal_en, boot_ack_rcv_signal_en, 9);
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register_bit!(interrupt_signal_en, card_interrupt_signal_en, 8);
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register_bit!(interrupt_signal_en, card_removal_signal_en, 7);
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register_bit!(interrupt_signal_en, card_insertion_signal_en, 6);
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register_bit!(interrupt_signal_en, buffer_read_ready_signal_en, 5);
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register_bit!(interrupt_signal_en, buffer_write_ready_signal_en, 4);
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register_bit!(interrupt_signal_en, dma_interrupt_signal_en, 3);
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register_bit!(interrupt_signal_en, block_gap_evt_signal_en, 2);
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register_bit!(interrupt_signal_en, transfer_complete_signal_en, 1);
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register_bit!(interrupt_signal_en, cmd_complete_signal_en, 0);
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register!(auto_cmd12_error_status, AutoCmd12ErrorStatus, RO, u32);
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register_bit!(
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auto_cmd12_error_status,
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cmd_not_issued_by_auto_cmd12_error,
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7
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);
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register_bit!(auto_cmd12_error_status, index_error, 4);
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register_bit!(auto_cmd12_error_status, end_bit_error, 3);
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register_bit!(auto_cmd12_error_status, crc_error, 2);
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register_bit!(auto_cmd12_error_status, timeout_error, 1);
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register_bit!(auto_cmd12_error_status, not_executed, 0);
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register!(capabilities, Capabilities, RO, u32);
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register_bit!(capabilities, spi_block_mode, 30);
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register_bit!(capabilities, spi_mode, 29);
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register_bit!(capabilities, support_64bit, 28);
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register_bit!(capabilities, interrupt_mode, 27);
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register_bit!(capabilities, voltage_1_8, 26);
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register_bit!(capabilities, voltage_3_0, 25);
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register_bit!(capabilities, voltage_3_3, 24);
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register_bit!(capabilities, suspend_resume, 23);
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register_bit!(capabilities, sdma, 22);
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register_bit!(capabilities, hgih_speed, 21);
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register_bit!(capabilities, adma2, 19);
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register_bit!(capabilities, extended_media_bus, 18);
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register_bits!(
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capabilities,
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/// Length = 2^(9 + v) bytes.
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max_block_len,
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u8,
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16,
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17
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);
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register_bit!(capabilities, timeout_clock_unit, 7);
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register!(max_current_capabilities, MaxCurrentCapabilities, RO, u32);
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register_bits!(max_current_capabilities, max_current_1_8v, u8, 16, 23);
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register_bits!(max_current_capabilities, max_current_3_0v, u8, 8, 15);
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register_bits!(max_current_capabilities, max_current_3_3v, u8, 0, 7);
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register!(force_event, ForceEvent, WO, u32);
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register_bit!(force_event, ceata_error, 29);
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register_bit!(force_event, target_response_error, 28);
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register_bit!(force_event, adma_error, 25);
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register_bit!(force_event, auto_cmd12_error, 24);
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register_bit!(force_event, current_limit_error, 23);
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register_bit!(force_event, data_end_bit_error, 22);
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register_bit!(force_event, data_crc_error, 21);
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register_bit!(force_event, data_timeout_error, 20);
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register_bit!(force_event, cmd_index_error, 19);
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register_bit!(force_event, cmd_end_bit_error, 18);
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register_bit!(force_event, cmd_crc_error, 17);
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register_bit!(force_event, cmd_timeout_error, 16);
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register_bit!(force_event, cmd_not_issued_by_auto_cmd12_error, 7);
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register_bit!(force_event, auto_cmd12_index_error, 4);
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register_bit!(force_event, auto_cmd12_end_bit_error, 3);
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register_bit!(force_event, auto_cmd12_crc_error, 2);
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register_bit!(force_event, auto_cmd12_timeout_error, 1);
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register_bit!(force_event, auto_cmd12_not_executed, 0);
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register!(adma_error_status, AdmaErrorStatus, RW, u32, 0b11);
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register_bit!(adma_error_status, length_mismatch_error, 2, WTC);
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register_bits_typed!(adma_error_status, error_state, u8, AdmaErrorState, 0, 1);
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register!(debug_selection, DebugSelection, WO, u32);
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register_bit!(debug_selection, debug_select, 0);
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register!(spi_interrupt_support, SpiInterruptSupport, RW, u32);
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register_bits!(
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spi_interrupt_support,
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/// There should be a problem with the documentation of this field.
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spi_int_support,
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u8,
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0,
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7
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);
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register!(misc_reg, MiscReg, RO, u32);
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register_bits!(misc_reg, vendor_version_num, u8, 24, 31);
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register_bits_typed!(misc_reg, spec_ver, u8, SpecificationVersion, 16, 23);
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register_bits!(
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misc_reg,
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/// Logical OR of interrupt signal and wakeup signal for each slot.
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slot_interrupt_signal,
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u8,
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0,
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7
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);
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@ -248,6 +248,7 @@ macro_rules! register_bit {
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$(#[$outer])*
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impl $mod_name::Write {
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/// Clear bit field. (WTC)
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#[allow(unused)]
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#[inline]
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pub fn $name(mut self) -> Self {
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