forked from M-Labs/zynq-rs
experiments: updated example.
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12669124a4
commit
02a2c4d1e3
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@ -15,7 +15,8 @@ use libboard_zynq::{
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clocks::source::{ArmPll, ClockSource, IoPll},
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clocks::source::{ArmPll, ClockSource, IoPll},
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clocks::Clocks,
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clocks::Clocks,
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print, println,
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print, println,
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sdio::sd_card::SdCard,
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mpcore,
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gic,
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smoltcp::{
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smoltcp::{
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iface::{EthernetInterfaceBuilder, NeighborCache, Routes},
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iface::{EthernetInterfaceBuilder, NeighborCache, Routes},
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time::Instant,
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time::Instant,
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@ -23,10 +24,9 @@ use libboard_zynq::{
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},
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},
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time::Milliseconds,
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time::Milliseconds,
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};
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};
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#[cfg(feature = "target_zc706")]
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use libboard_zynq::ps7_init;
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use libcortex_a9::{
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use libcortex_a9::{
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mutex::Mutex,
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mutex::Mutex,
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sync_channel::{Sender, Receiver},
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sync_channel,
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sync_channel,
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};
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};
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use libregister::RegisterR;
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use libregister::RegisterR;
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@ -37,6 +37,9 @@ use log::{info, warn};
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const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
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const HWADDR: [u8; 6] = [0, 0x23, 0xde, 0xea, 0xbe, 0xef];
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static mut CORE1_REQ: (Sender<usize>, Receiver<usize>) = sync_channel!(usize, 10);
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static mut CORE1_RES: (Sender<usize>, Receiver<usize>) = sync_channel!(usize, 10);
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#[no_mangle]
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#[no_mangle]
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pub fn main_core0() {
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pub fn main_core0() {
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// zynq::clocks::CpuClocks::enable_io(1_250_000_000);
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// zynq::clocks::CpuClocks::enable_io(1_250_000_000);
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@ -83,26 +86,6 @@ pub fn main_core0() {
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clocks.cpu_1x()
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clocks.cpu_1x()
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);
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);
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// commented out due to OCM full
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// let sd = libboard_zynq::sdio::SDIO::sdio0(true);
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// // only test SD card if it is inserted
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// if sd.is_card_inserted() {
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// let result = SdCard::from_sdio(sd);
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// match &result {
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// Ok(_) => info!("OK!"),
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// Err(a) => info!("{}", a),
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// };
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// const SIZE: usize = 512 * 2 + 1;
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// let mut sd_card = result.unwrap();
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// if false {
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// let buffer: [u8; SIZE] = [5; SIZE];
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// sd_card.write_block(0x0, 2, &buffer).unwrap();
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// }
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// let mut buffer: [u8; SIZE] = [0; SIZE];
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// sd_card.read_block(0 /*0x1*/, 2, &mut buffer[1..]).unwrap();
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// info!("buffer = {:?}", &buffer[..]);
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// }
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let mut flash = zynq::flash::Flash::new(200_000_000).linear_addressing_mode();
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let mut flash = zynq::flash::Flash::new(200_000_000).linear_addressing_mode();
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let flash_ram: &[u8] = unsafe { core::slice::from_raw_parts(flash.ptr(), flash.size()) };
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let flash_ram: &[u8] = unsafe { core::slice::from_raw_parts(flash.ptr(), flash.size()) };
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for i in 0..=1 {
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for i in 0..=1 {
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@ -160,20 +143,21 @@ pub fn main_core0() {
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flash = flash_io.stop();
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flash = flash_io.stop();
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}
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}
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let core1 = boot::Core1::start(false);
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boot::Core1::start(false);
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let (mut core1_req, rx) = sync_channel!(usize, 10);
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let core1_req = unsafe { &mut CORE1_REQ.0 };
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*CORE1_REQ.lock() = Some(rx);
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let core1_res = unsafe { &mut CORE1_RES.1 };
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let (tx, mut core1_res) = sync_channel!(usize, 10);
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let mut interrupt_controller = gic::InterruptController::new(mpcore::RegisterBlock::new());
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*CORE1_RES.lock() = Some(tx);
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interrupt_controller.enable_interrupts();
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task::block_on(async {
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task::block_on(async {
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for i in 0..10 {
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for i in 0..10 {
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// this interrupt would cause core1 to reset.
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interrupt_controller.send_sgi(gic::InterruptId(0), gic::CPUCore::Core1.into());
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core1_req.async_send(i).await;
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core1_req.async_send(i).await;
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let j = core1_res.async_recv().await;
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let j = core1_res.async_recv().await;
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println!("{} -> {}", i, j);
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println!("{} -> {}", i, j);
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}
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}
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});
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});
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core1.disable();
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let eth = zynq::eth::Eth::default(HWADDR.clone());
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let eth = zynq::eth::Eth::default(HWADDR.clone());
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println!("Eth on");
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println!("Eth on");
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@ -198,9 +182,6 @@ pub fn main_core0() {
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.neighbor_cache(neighbor_cache)
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.neighbor_cache(neighbor_cache)
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.finalize();
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.finalize();
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#[cfg(feature = "target_zc706")]
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ps7_init::report_differences();
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Sockets::init(32);
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Sockets::init(32);
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const TCP_PORT: u16 = 19;
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const TCP_PORT: u16 = 19;
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@ -267,24 +248,15 @@ pub fn main_core0() {
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})
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})
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}
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}
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static CORE1_REQ: Mutex<Option<sync_channel::Receiver<usize>>> = Mutex::new(None);
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static CORE1_RES: Mutex<Option<sync_channel::Sender<usize>>> = Mutex::new(None);
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static DONE: Mutex<bool> = Mutex::new(false);
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static DONE: Mutex<bool> = Mutex::new(false);
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#[no_mangle]
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#[no_mangle]
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pub fn main_core1() {
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pub fn main_core1() {
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println!("Hello from core1!");
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println!("Hello from core1!");
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let mut interrupt_controller = gic::InterruptController::new(mpcore::RegisterBlock::new());
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let mut req = None;
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interrupt_controller.enable_interrupts();
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while req.is_none() {
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let req = unsafe { &mut CORE1_REQ.1 };
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req = CORE1_REQ.lock().take();
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let res = unsafe { &mut CORE1_RES.0 };
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}
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let req = req.unwrap();
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let mut res = None;
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while res.is_none() {
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res = CORE1_RES.lock().take();
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}
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let mut res = res.unwrap();
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for i in req {
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for i in req {
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res.send(i * i);
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res.send(i * i);
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