5432.tex

@@ -1,10 +1,11 @@
 \input{preamble.tex}
-\graphicspath{{images/5432}{images}}
+\input{shared/dactino.tex}
+\graphicspath{{images/5432}, {images}}
 
 \title{5432 DAC Zotino}
 \author{M-Labs Limited}
-\date{January 2022}
-\revision{Revision 2}
+\date{January 2025}
+\revision{Revision 3}
 \companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
 
 \begin{document}
@@ -14,7 +15,7 @@
 
     \begin{itemize}
         \item{32-channel DAC}
-\item{16-bits resolution}
+        \item{16-bit resolution}
         \item{1 MSPS shared between all channels}
         \item{Output voltage $\pm$10V}
         \item{HD68 connector}
@@ -29,10 +30,7 @@
         \item{Driving DC electrodes in ion traps}
     \end{itemize}
 
-\section{General Description}
-The 5432 Zotino is a 4hp EEM module and part of the ARTIQ/Sinara family. It adds digital-analog conversion capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC.
-
-It provides four groups of eight analog channels each, exposed by one HD68 connector. Each channel supports output voltage from -10 V to 10 V. All channels can be updated simultaneously. Channels can broken out to BNC, SMA or MCX by adding external 5518 BNC-IDC, 5528 SMA-IDC or 5538 MCX-IDC cards.
+\generaldescription{5432 DAC Zotino}{high-speed 5632 DAC Fastino}
 
 % Switch to next column
 \vfill\break
@@ -224,23 +222,28 @@ Far-end crosstalk was measured using the following setup\repeatfootnote{zotino21
         \caption{Step crosstalk}
     \end{figure}
 
-\newpage
+\section{LEDs}
 
-\codesection{5432 DAC Zotino}
-
-\subsection{Setting output voltage}
-The following example initializes the Zotino card, then emits 1.0 V, 2.0 V, 3.0 V and 4.0 V at channels 0, 1, 2, and 3 respectively. Voltages of all 4 channels are updated simultaneously with the use of \texttt{set\char`_dac()}.
-
-\inputcolorboxminted{firstline=11,lastline=22}{examples/zotino.py}
+    5432 DAC Zotino provides eight user LEDs in the front panel. These are directly accessible in ARTIQ RTIO.
 
 \newpage
 
-\subsection{Triangular wave}
-Generates a triangular waveform at 10 Hz, 16 V peak-to-peak. Timing accuracy of the RTIO system can be demonstrated by the precision of the frequency.
+\sysdescsection
 
-Import \texttt{scipy.signal} and \texttt{numpy} modules to run this example.
+    5432 DAC Zotino should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
 
-\inputcolorboxminted{firstline=30,lastline=49}{examples/zotino.py}
+    \begin{tcolorbox}[colback=white]
+        \begin{minted}{json}
+            {
+                "type": "zotino",
+                "ports": [0]
+            }
+        \end{minted}
+    \end{tcolorbox}
+
+    Replace 0 with the EEM port used on the core device. Any port may be used.
+
+\codesectiondactino{5432 DAC Zotino}{Zotino}{zotino.py}
 
 \ordersection{5432 DAC Zotino}
 

5632.tex

@@ -0,0 +1,163 @@
+\input{preamble.tex}
+\input{shared/dactino.tex}
+\graphicspath{{images/5632}, {images}}
+
+\title{5632 DAC Fastino}
+\author{M-Labs Limited}
+\date{January 2025}
+\revision{Revision 1}
+\companylogo{\includegraphics[height=0.73in]{artiq_sinara.pdf}}
+
+\begin{document}
+\maketitle
+
+\section{Features}
+
+    \begin{itemize}
+        \item{32-channel fast DAC}
+        \item{16-bit resolution}
+        \item{2.55 MSPS per channel}
+        \item{Output voltage $\pm$10V}
+        \item{Gateware CIC interpolation}
+        \item{HD68 connector}
+        \item{Can be broken out to BNC/SMA/MCX}
+    \end{itemize}
+
+\section{Applications}
+
+    \begin{itemize}
+        \item{Controlling setpoints of PID controllers for laser power stabilization}
+        \item{Low-frequency arbitrary waveform generation}
+        \item{Driving DC electrodes in ion traps}
+    \end{itemize}
+
+\generaldescription{5632 DAC Fastino}{slower 5432 DAC Zotino}
+
+% Switch to next column
+\vfill\break
+
+%\begin{figure}[h]
+%    \centering
+%    \scalebox{1.15}{
+%    \begin{circuitikz}[european, every label/.append style={align=center}]
+%        \begin{scope}[]
+%            % if applicable
+%        \end{scope}
+%    \end{circuitikz}
+%    }
+
+%    \caption{Simplified Block Diagram}
+%\end{figure}
+
+\begin{figure}[hbt!]
+    \centering
+    \includegraphics[height=2.25in]{photo5632.jpg}
+    \caption{Fastino card}
+    \includegraphics[height=3in, angle=90]{fp5632.pdf}
+    \caption{Fastino front panel}
+\end{figure}
+
+% For wide tables, a single column layout is better. It can be switched
+% page-by-page.
+\onecolumn
+
+\sourcesection{5632 DAC Fastino}{https://github.com/sinara-hw/Fastino}
+
+\section{Electrical Specifications}
+
+    % \hypersetup{hidelinks}
+    % \urlstyle{same}
+    These specifications are based on the datasheet of the DAC IC
+    (AD5542ABCPZ\footnote{\label{dac}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/AD5512A_5542A.pdf}}),
+    and various information from the Sinara wiki\footnote{\label{fastino_wiki}\url{https://github.com/sinara-hw/Fastino/wiki}}.
+
+    \begin{table}[h]
+    \centering
+    \begin{threeparttable}
+    \caption{Output Specifications}
+    \begin{tabularx}{0.8\textwidth}{l | c c c | c | X}
+        \thickhline
+        \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+        \textbf{Unit} & \textbf{Conditions} \\
+        \hline
+        Output voltage & -10 & & 10 & V & \\
+        % \hline is this accurate here?
+        % Output impedance\repeatfootnote{zotino_wiki} & \multicolumn{4}{c|}{470 $\Omega$ $||$ 2.2nF} & \\
+        \hline
+        Resolution\repeatfootnote{dac} & & 16 & & bits & \\
+        \hline
+        Settling time\repeatfootnote{dac} & & 1 & & \textmu s & \\
+        \hline
+        Temperature coefficient\repeatfootnote{fastino_wiki} & & & 7 & ppm & \\
+        %\hline is this accurate here?
+        %3dB bandwidth\repeatfootnote{zotino_wiki} & & 75 & & kHz & \\
+        \thickhline
+    \end{tabularx}
+    \end{threeparttable}
+    \end{table}
+
+    The following table records cross-talk and transient behavior by Fastino, collected in various Sinara issues, see spur analysis\footnote{\label{fastino56}\url{https://github.com/sinara-hw/Fastino/issues/56}}, cross-talk\footnote{\url{https://github.com/sinara-hw/Fastino/issues/85}}, and noise summary\footnote{\url{https://github.com/sinara-hw/Fastino/issues/51}}. DAC output during output noise measurement was 6.875 V, updating continuously, channel 27 used for recording.
+
+    \begin{table}[h]
+    \centering
+    \begin{threeparttable}
+    \caption{Electrical Characteristics}
+    \begin{tabularx}{0.8\textwidth}{l | c c c | c | X}
+        \thickhline
+        \textbf{Parameter} & \textbf{Min.} & \textbf{Typ.} & \textbf{Max.} &
+        \textbf{Unit} & \textbf{Conditions / Comments} \\
+        \hline
+        DC cross-talk & & & -65 & dBmV & \\
+        \hline
+        % Is this the same measurement as 'Output noise'?
+        Broadband noise (??) & & & & & \\
+        \hspace{18mm} @ 100 kHz & & 14 & & nV/rtHz & \\
+        \hspace{18mm} @ 1 MHz & & 56 & & nV/rtHz & \\
+        \hline
+        Output noise & & & & & \\
+        \hspace{18mm} @ 500 kHz & & 60 & 80 & nV/rtHz & \\
+        \hspace{18mm} @ 2 MHz & & & 12 & nV/rtHz & \\
+        \hspace{18mm} @ 10 MHz & & & 4 & nV/rtHz & \\
+        \hline
+        Spur-free range & 0.1 & & 5 & MHz & Correctly configured\repeatfootnote{fastino56} \\
+        Digital update spurs & & 560 & & nVrm & @ 2.55MHz \\
+        \thickhline
+    \end{tabularx}
+    \end{threeparttable}
+    \end{table}
+
+    % Is it worth recounting spur summary issue here?
+
+\section{LEDs}
+
+    5632 DAC Fastino provides eight user LEDs in the front panel. These are directly accessible in the ARTIQ RTIO. Four additional LEDs indicate, respectively, power good (\texttt{PG}), ??? (\texttt{FD}), overtemperature (\texttt{OT}), and gateware or initialization error (\texttt{ERR}).
+
+\sysdescsection
+
+    5632 DAC Fastino should be entered in the \texttt{peripherals} list of the corresponding core device in the following format:
+
+    \begin{tcolorbox}[colback=white]
+        \begin{minted}{json}
+            {
+                "type": "fastino",
+                "ports": [0],
+                "log2_width": 0 // select 0 to 5, default is 0
+            }
+        \end{minted}
+    \end{tcolorbox}
+
+    Replace 0 with the EEM port used on the core device. Any port may be used on the core device side. Despite providing two EEM ports, Fastino only requires one of two under ARTIQ control. This should always be \texttt{EEM0}. If connected, \texttt{EEM1} will be ignored.
+
+    The \texttt{log2\_width} field accepts a number from 0 to 5 inclusive and represents (in powers of two) the number of DAC channels packed into a single RTIO write (1 to 32). This allows and defines the use of \texttt{set\_group()} functions rather than \texttt{set\_dac()} as in examples given below.
+
+\codesectiondactino{5632 DAC Fastino}{Fastino}{fastino.py}
+
+    \subsection{CIC interpolators}
+
+    Fastino gateware features dynamically configurable CIC (cubic B-spline) interpolators, defined individually by channel, with interpolation rates from 1 (2.55 MSPS) to 65536 (39 SPS). For more details, see manual documentation on ARTIQ driver functions \texttt{stage\_cic} and \texttt{apply\_cic}.
+
+\ordersection{5632 DAC Fastino}
+
+\finalfootnote
+
+\end{document}

examples/fastino.py

@@ -0,0 +1,50 @@
+from artiq.experiment import *
+from scipy import signal
+import numpy
+
+# duplicated from zotino.py with name replaced
+class Voltage(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.fastino = self.get_device("fastino0")
+
+    def prepare(self):
+        self.channels = [0, 1, 2, 3]
+        self.voltages = [1.0, 2.0, 3.0, 4.0]
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.core.break_realtime()
+        self.fastino.init()
+
+        delay(1*ms)
+        self.fastino.set_dac(self.voltages, self.channels)
+
+# duplicated from zotino.py with name replaced
+class TriangularWave(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.zotino = self.get_device("fastino0")
+
+    def prepare(self):
+        self.period = 0.1*s
+        self.sample = 128
+        t = numpy.linspace(0, 1, self.sample)
+        self.voltages = 8*signal.sawtooth(2*numpy.pi*t, 0.5)
+        self.interval = self.period/self.sample
+
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.core.break_realtime()
+        self.fastino.init()
+
+        delay(1*ms)
+
+        counter = 0
+        while True:
+            self.fastino.set_dac([self.voltages[counter]], [0])
+            counter = (counter + 1) % self.sample
+            delay(self.interval)
+

shared/dactino.tex

@@ -0,0 +1,31 @@
+\newcommand{\generaldescription}[2] {
+
+    \section{General Description}
+
+    The #1 is a 4hp EEM module, part of the ARTIQ/Sinara family. It adds digital-analog conversion capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC. It is closely related to the #2 and the two cards share a compatible output interface.
+
+    It provides four groups of eight analog channels each, exposed by one HD68 connector. Each channel supports output voltage from -10 V to 10 V. All channels can be updated simultaneously. Channels can broken out to BNC, SMA or MCX by adding external 5518 BNC-IDC, 5528 SMA-IDC or 5538 MCX-IDC cards.
+}
+
+\newcommand{\codesectiondactino}[3] {
+
+    \codesection{#1}
+
+    \subsection{Setting output voltage}
+
+    The following example initializes the #2 card, then emits 1.0 V, 2.0 V, 3.0 V and 4.0 V at channels 0, 1, 2, and 3 respectively. Voltage of all 4 channels is updated simultaneously with the use of \texttt{set\char`_dac()}.
+
+    \inputcolorboxminted{firstline=11,lastline=22}{examples/#3}
+
+    % this new page works for both datasheets, but may not if sections are added
+\newpage
+
+    \subsection{Triangular wave}
+
+    The following example generates a triangular waveform at 10 Hz, 16 V peak-to-peak. Timing accuracy of the RTIO system can be demonstrated by the precision of the frequency.
+
+    Import \texttt{scipy.signal} and \texttt{numpy} modules to run this example.
+
+    \inputcolorboxminted{firstline=30,lastline=49}{examples/#3}
+
+}