WIP: 5432, 5632: add Fastino #79

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architeuthis wants to merge 7 commits from architeuthis/datasheets:zotino into master
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PDFs attached. Fastino specifications are taken more or less unquestioned from wiki/various issues/etc., feedback and sanity checking appreciated. Example code is here just duplicated from zotino.py, but with name changed to avoid confusion; it'd potentially be cleaner to have a single example, but I wasn't sure what an appropriate general name would be (dac.py ? xxtino.py ?). Or it can just be duplicated.

PDFs attached. Fastino specifications are taken more or less unquestioned from wiki/various issues/etc., feedback and sanity checking appreciated. Example code is here just duplicated from `zotino.py`, but with name changed to avoid confusion; it'd potentially be cleaner to have a single example, but I wasn't sure what an appropriate general name would be (`dac.py` ? `xxtino.py` ?). Or it can just be duplicated.
504 KiB
346 KiB
architeuthis added 7 commits 2025-02-01 08:23:24 +08:00
morgan reviewed 2025-02-04 13:10:17 +08:00
@ -141,0 +134,4 @@
% \hypersetup{hidelinks}
% \urlstyle{same}
These specifications are based on the datasheet of the DAC IC
(AD5372BCPZ\footnote{\label{dac}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/AD5372\_5373.pdf}}),
Member

nitpick: use AD5372 instead of AD5372BCPZ, as extra alphabets denote the packages/version number which is not essential

nitpick: use AD5372 instead of AD5372BCPZ, as extra alphabets denote the packages/version number which is not essential
@ -224,2 +167,2 @@
\caption{Step crosstalk}
\end{figure}
\begin{threeparttable}
\caption{Electrical Characteristics}
Member

we should also include DAC's sampling rate here

we should also include DAC's sampling rate here
@ -0,0 +68,4 @@
% \hypersetup{hidelinks}
% \urlstyle{same}
These specifications are based on the datasheet of the DAC IC
(AD5542ABCPZ\footnote{\label{dac}\url{https://www.analog.com/media/en/technical-documentation/data-sheets/AD5512A_5542A.pdf}}),
Member

same as above, use AD5544 instead

same as above, use AD5544 instead
@ -0,0 +74,4 @@
\begin{table}[h]
\centering
\begin{threeparttable}
\caption{Output Specifications}
Member

we should also include

we should also include - DAC's sampling rate - power consumption (see https://github.com/sinara-hw/Fastino/issues/14#issuecomment-531811275)
@ -0,0 +90,4 @@
\hline
Temperature coefficient\repeatfootnote{fastino_wiki} & & & 7 & ppm & \\
%\hline is this accurate here?
%3dB bandwidth\repeatfootnote{zotino_wiki} & & 75 & & kHz & \\
Member
output bandwidth is 500 kHz (see https://github.com/sinara-hw/Fastino/issues/4#issuecomment-531710790)
@ -0,0 +112,4 @@
% Is this the same measurement as 'Output noise'?
Broadband noise (??) & & & & & \\
\hspace{18mm} @ 100 kHz & & 14 & & nV/rtHz & \\
\hspace{18mm} @ 1 MHz & & 56 & & nV/rtHz & \\
Member

Yes it is also measuring the noise PSD, but it should be 56 nV/rtHz @ 100kHz and 14 nV/rtHz @ 1MHz (see https://github.com/sinara-hw/Fastino/issues/85#issuecomment-776057649). BUT it should not be merged into the output noise data as they used different BW setting on their spectrum analyzer (1kHz vs 6.9kHz).
(FYI dBV -> nV/rtHz convertion foruma)

Yes it is also measuring the noise PSD, but it should be 56 nV/rtHz @ 100kHz and 14 nV/rtHz @ 1MHz (see https://github.com/sinara-hw/Fastino/issues/85#issuecomment-776057649). BUT it should not be merged into the output noise data as they used different BW setting on their spectrum analyzer (1kHz vs 6.9kHz). (FYI [dBV -> nV/rtHz convertion foruma](https://electronics.stackexchange.com/questions/601587/converting-db-vs-frequency-to-v-sqrthz-frequency))
@ -0,0 +126,4 @@
\end{threeparttable}
\end{table}
% Is it worth recounting spur summary issue here?
Member

you are talking about the switching power supply coupling issue?

you are talking about the [switching power supply coupling issue](https://github.com/sinara-hw/Fastino/issues/56)?
@ -0,0 +130,4 @@
\section{LEDs}
5632 DAC Fastino provides eight user LEDs in the front panel. These are directly accessible in the ARTIQ RTIO. Four additional LEDs indicate, respectively, power good (\texttt{PG}), ??? (\texttt{FD}), overtemperature (\texttt{OT}), and gateware or initialization error (\texttt{ERR}).
Member

I think is FPGA DONE, the schematic shows LED is connected by the CDONE NET
image

I think is FPGA DONE, the schematic shows LED is connected by the CDONE NET ![image](/attachments/6c07a30a-b2ac-4994-8d77-bcb2f5188ec2)
@ -0,0 +4,4 @@
The #1 is a 4hp EEM module, part of the ARTIQ/Sinara family. It adds digital-analog conversion capabilities to carrier cards such as 1124 Kasli and 1125 Kasli-SoC. It is closely related to the #2 and the two cards share a compatible output interface.
It provides four groups of eight analog channels each, exposed by one HD68 connector. Each channel supports output voltage from -10 V to 10 V. All channels can be updated simultaneously. Channels can broken out to BNC, SMA or MCX by adding external 5518 BNC-IDC, 5528 SMA-IDC or 5538 MCX-IDC cards.
Member

should be "eight analog channels , each exposed by"

should be "eight analog channels **, each** exposed by"
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Reference: sinara-hw/datasheets#79
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