2118-2128: add TTLClockGen example

2118-2128.tex

@@ -508,10 +508,19 @@ The channel should be configured as output in both the gateware and hardware.
 
 \newpage
 
+\subsection{Sub-coarse-RTIO-cycle pulse}
+With the use of the ARTIQ RTIO, only 1 event can be enqueued per coarse RTIO cycle, which is typically 8ns.
+Therefore, to emit a pulse that is less than 8ns, additional delay is needed such that the \texttt{ttl.on()} \& \texttt{ttl.off()} event are submitted at different coarse RTIO cycles.
+The TTL pulse parameter must satisfy the minimum pulse width stated in the electircal specifications.
+
+\inputcolorboxminted{firstline=88,lastline=92}{examples/ttl.py}
+
 \subsection{Morse code}
 This example demonstrates some basic algorithmic features of the ARTIQ-Python language.
 \inputcolorboxminted{firstline=22,lastline=39}{examples/ttl.py}
 
+\newpage
+
 \subsection{Counting rising edges in a 1ms window}
 The channel should be configured as input in both the gateware and hardware.
 \inputcolorboxminted{firstline=47,lastline=52}{examples/ttl.py}
@@ -520,12 +529,22 @@ This example code uses the software counter, which has a maximum count rate of a
 If the gateware counter is enabled on the TTL channel, it can typically count up to 125 million events per second:
 \inputcolorboxminted{firstline=60,lastline=65}{examples/ttl.py}
 
-\newpage
+To count falling edges or both rising \& falling edges, use \texttt{gate\char`_falling()} or \texttt{gate\char`_both()}.
 
 \subsection{Responding to an external trigger}
 One channel needs to be configured as input, and the other as output.
 \inputcolorboxminted{firstline=74,lastline=80}{examples/ttl.py}
 
+\subsection{62.5 MHz clock signal generation}
+A TTL channel can be configured as a \texttt{ClockGen} channel, which generates a periodic clock signal.
+Each channel has a phase accumulator operating on the RTIO clock, where it is incremented by the frequency tuning word at each coarse RTIO cycle.
+Therefore, jitter should be expected when the desired frequency cannot be obtained by dividing the coarse RTIO clock frequency with a power of 2. \\
+
+Typically, with the coarse RTIO clock at 125 MHz, a \texttt{ClockGen} channel can generate up to 62.5 MHz.
+\inputcolorboxminted{firstline=100,lastline=103}{examples/ttl.py}
+
+\newpage
+
 \section{Ordering Information}
 To order, please visit \url{https://m-labs.hk} and select the 2118 BNC-TTL/2128 SMA-TTL in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
 

4410-4412.tex

@@ -691,6 +691,7 @@ Harmonic content of the DDS signals from 4410 DDS Urukul is tabulated below\foot
 
 \end{multicols}
 
+\newpage
 \section{Urukul Mode Configurations}
 Mode of operation is specified by a DIP switch.
 The DIP switch can be found at the top right corner of the card.
@@ -720,6 +721,28 @@ The following table summarizes the required setting for each mode.
 
 \end{multicols}
 
+Note for Default mode: Switching on DIP Switch 3 enables the options that distribute the synchronization signals externally.
+However, ARTIQ \& the core device (Kasli/Kasli-SoC) do not interact with these signals.
+
+\section{Urukul 1-EEM/2-EEM Modes}
+4410/4412 DDS Urukul can operate with either 1 or 2 EEM connections.
+It is in 1-EEM mode when only EEM0 is connected, 2-EEM mode when both EEM0 \& EEM1 are connected.
+2-EEM mode provides these additional features in comparison to 1-EEM mode.
+\begin{itemize}
+    \item 1 ns temporal resolution RF switches \\
+    Without EEM1, the only way to access the switches is through the CPLD using SPI. \\
+    With EEM1, RF switches can be controlled as a TTL output through the LVDS transceiver.
+    1 ns temporal resolution is achieved using the ARTIQ RTIO system.
+
+    \item SU-Servo (4410 DDS Urukul feature) \\
+    SU-Servo requires both EEM0 \& EEM1 to control multiple DDS channels simultaneously using the QSPI interface.
+
+    \item Distribute synchronization signals from Urukul (4410 DDS Urukul feature) \\
+    Synchronization signals can only be distributed externally through EEM1.
+    ARTIQ \& the core device (Kasli/Kasli-SoC) will never interact with these signals.
+
+\end{itemize}
+
 \newpage
 
 \section{Example ARTIQ code}

examples/ttl.py

@@ -78,3 +78,26 @@ class ExternalTrigger(EnvExperiment):
         timestamp_mu = self.ttlin.timestamp_mu(gate_end_mu)
         at_mu(timestamp_mu + self.core.seconds_to_mu(10*ms))
         self.ttlout.pulse(1*us)
+
+
+class ShortPulse(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.ttl0 = self.get_device("ttl0")
+    
+    @kernel
+    def run(self):
+        self.core.reset()
+        delay(6*ns)             # Coarse RTIO period: 0 - 7  ns
+        self.ttl0.pulse(3*ns)   # Coarse RTIO period: 8 - 15 ns
+
+
+class ClockGen(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.ttl0 = self.get_device("ttl0")
+    
+    @kernel
+    def run(self):
+        self.core.reset()
+        self.ttl0.set(62.5*MHz)