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occheung | d387006656 | |
occheung | 69696899ac | |
occheung | 8ce5cca85e | |
occheung | d6d29c89a1 | |
occheung | a7dfa03a21 |
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@ -607,13 +607,23 @@ Typically, with the coarse RTIO clock at 125 MHz, a \texttt{ClockGen} channel ca
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\inputcolorboxminted{firstline=72,lastline=75}{examples/ttl.py}
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\newpage
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\subsection{Maximum Sustained Event Separation}
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The maximum sustained event separation is the least amount of time separation between input gated events, in which all gated edges can be continuously \& reliabily timestamped by the RTIO system without causing \texttt{RTIOOverflow} exceptions.
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\subsection{Minimum Sustained Event Separation}
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The minimum sustained event separation is the least amount of time separation between input gated events, in which all gated edges can be continuously \& reliabily timestamped by the RTIO system without causing \texttt{RTIOOverflow} exceptions.
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The following \texttt{run()} function finds the separation by approximating the time of running \texttt{timestamp\char`_mu()} as a constant. Import the \texttt{time} library to use \texttt{time.sleep()}.
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\inputcolorboxminted{firstline=60,lastline=92}{examples/ttl_in.py}
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\inputcolorboxminted{firstline=63,lastline=98}{examples/ttl_in.py}
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The result fluctuates at around 650ns with Kasli v1.1.
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\begin{center}
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\begin{table}[H]
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\captionof{table}{Minimum sustained event separation of different carrier}
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\centering
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\begin{tabular}{|c|c|c|}
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\hline
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Carrier & Kasli v1.1 & Kasli-SoC \\ \hline
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Duration & 650 ns & 600 ns \\ \hline
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\end{tabular}
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\end{table}
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\end{center}
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\section{Ordering Information}
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To order, please visit \url{https://m-labs.hk} and select the 2118 BNC-TTL/2128 SMA-TTL in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.
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@ -51,6 +51,9 @@ class ExternalTrigger(EnvExperiment):
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self.ttlout.pulse(1*us)
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import time
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class MeanTimestampDuration(EnvExperiment):
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def build(self):
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self.setattr_device("core")
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@ -72,7 +75,10 @@ class MeanTimestampDuration(EnvExperiment):
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# Guarantee t0 > gate_end_mu
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# Otherwise timestamp_mu may wait for pulses till gate_end_mu
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self.rpc_sleep(1*ms)
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rtio_time_mu = self.core.get_rtio_counter_mu()
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sleep_mu = float(gate_end_mu - rtio_time_mu)
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self.rpc_sleep(self.core.mu_to_seconds(sleep_mu))
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t0 = self.core.get_rtio_counter_mu()
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while self.ttlin.timestamp_mu(gate_end_mu) >= 0:
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pass
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