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4410-4412: add unit when calling set_att()

This commit is contained in:
occheung 2021-12-08 12:19:31 +08:00
parent 2127697fe6
commit b538ef7858
1 changed files with 4 additions and 3 deletions
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7
4410-4412.tex
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@ -428,6 +428,7 @@ def run(self):
self.cpld.init() self.cpld.init()
self.dds0.init() self.dds0.init()
self.dds0.cfg_sw(True) self.dds0.cfg_sw(True)
self.dds0.set_att(6.*dB)
self.dds0.set(10*MHz) self.dds0.set(10*MHz)
\end{minted} \end{minted}
@ -442,11 +443,11 @@ def run(self):
self.dds0.init() self.dds0.init()
self.dds0.cfg_sw(True) self.dds0.cfg_sw(True)
self.dds0.set_phase_mode(PHASE_MODE_TRACKING) self.dds0.set_phase_mode(PHASE_MODE_TRACKING)
self.dds0.set_att(6.) self.dds0.set_att(6.*dB)
self.dds1.init() self.dds1.init()
self.dds1.cfg_sw(True) self.dds1.cfg_sw(True)
self.dds1.set_phase_mode(PHASE_MODE_TRACKING) self.dds1.set_phase_mode(PHASE_MODE_TRACKING)
self.dds1.set_att(6.) self.dds1.set_att(6.*dB)
self.dds0.set(frequency=10*MHz, phase=0.0) self.dds0.set(frequency=10*MHz, phase=0.0)
self.dds1.set(frequency=10*MHz, phase=0.25) # 0.25 turns phase offset self.dds1.set(frequency=10*MHz, phase=0.25) # 0.25 turns phase offset
@ -470,7 +471,7 @@ def prepare(self):
def init_dds(self, dds): def init_dds(self, dds):
self.core.break_realtime() self.core.break_realtime()
dds.init() dds.init()
dds.set_att(6.) dds.set_att(6.*dB)
dds.cfg_sw(True) dds.cfg_sw(True)
@kernel @kernel