2118-2128: add TTLClockGen example

This commit is contained in:
occheung 2022-06-07 16:01:18 +08:00
parent 9bd1412d9c
commit ac639b9d1e
2 changed files with 21 additions and 0 deletions

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@ -535,6 +535,16 @@ To count falling edges or both rising \& falling edges, use \texttt{gate\char`_f
One channel needs to be configured as input, and the other as output.
\inputcolorboxminted{firstline=74,lastline=80}{examples/ttl.py}
\subsection{62.5 MHz clock signal generation}
A TTL channel can be configured as a \texttt{ClockGen} channel, which generates a periodic clock signal.
Each channel has a phase accumulator operating on the RTIO clock, where it is incremented by the frequency tuning word at each coarse RTIO cycle.
Therefore, jitter should be expected when the desired frequency cannot be obtained by dividing the coarse RTIO clock frequency with a power of 2. \\
Typically, with the coarse RTIO clock at 125 MHz, a \texttt{ClockGen} channel can generate up to 62.5 MHz.
\inputcolorboxminted{firstline=100,lastline=103}{examples/ttl.py}
\newpage
\section{Ordering Information}
To order, please visit \url{https://m-labs.hk} and select the 2118 BNC-TTL/2128 SMA-TTL in the ARTIQ Sinara crate configuration tool. The card may also be ordered separately by writing to \url{mailto:sales@m-labs.hk}.

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@ -90,3 +90,14 @@ class ShortPulse(EnvExperiment):
self.core.reset()
delay(6*ns) # Coarse RTIO period: 0 - 7 ns
self.ttl0.pulse(3*ns) # Coarse RTIO period: 8 - 15 ns
class ClockGen(EnvExperiment):
def build(self):
self.setattr_device("core")
self.ttl0 = self.get_device("ttl0")
@kernel
def run(self):
self.core.reset()
self.ttl0.set(62.5*MHz)