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7210 update fixes

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architeuthidae 2024-10-28 21:57:20 +01:00
parent 4aeaaea8db
commit 5a426bd299
1 changed files with 4 additions and 4 deletions
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7210.tex
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@ -249,9 +249,9 @@ Specifications are derived based on the datasheets of the clock buffer (ADCLK950
\hspace{3mm} Peak-to-peak voltage & 0.40 & & 2.40 & V\textsubscript{p-p} & \\
\hspace{3mm} Frequency & 10 & & 4000 & MHz & \\
\hline
Clock output
& & 0.8 & & V\textsubscript{p-p} & \multirow{3}{*}{50\textOmega~load, 100 MHz} \\
& & 5 & & dBm & \\
Clock output & & & & & \\
\hspace{3mm} Peak-to-peak voltage & & 0.8 & & V\textsubscript{p-p} & \multirow{3}{*}{50\textOmega~load, 100 MHz} \\
\hspace{3mm} Power & & 5 & & dBm & \\
\thickhline
\end{tabularx}
\end{threeparttable}
@ -276,7 +276,7 @@ Performance measured against 100 MHz Wenzel Quartz, phase-locked to 10MHz Wenzel
\end{figure}
\section{Selecting Clock Source}
Clock input can be supplied to 7210 Clocker using either the internal MMCX connector or the external SMA connector on the front panel. The selection of clock input is configurable by an SPDT switch, located between the MMCX input connector (\texttt{INT CLK IN}) and the MMCX output connectors. See Figure 4.
Clock input can be supplied to 7210 Clocker using either the internal MMCX connector or the external SMA connector on the front panel. The selection of clock input is configurable by an SPDT switch, located between the MMCX input connector (\texttt{INT CLK IN}) and the MMCX output connectors. See Figure 5.
\begin{multicols}{2}
Either \texttt{INT} or \texttt{EXT} can be selected.