2022-01-20 16:43:41 +08:00
|
|
|
from artiq.experiment import *
|
|
|
|
|
|
|
|
|
|
|
|
class SUServoExample(EnvExperiment):
|
|
|
|
def build(self):
|
|
|
|
self.setattr_device("core")
|
|
|
|
self.suservo = self.get_device("suservo0")
|
2022-01-20 16:48:55 +08:00
|
|
|
self.suschannel0 = self.get_device("suservo0_ch0")
|
2022-01-20 16:43:41 +08:00
|
|
|
|
|
|
|
@kernel
|
|
|
|
def run(self):
|
|
|
|
self.core.reset()
|
|
|
|
self.core.break_realtime()
|
|
|
|
self.suservo.init()
|
|
|
|
self.suservo.set_pgia_mu(0, 0) # unity gain
|
|
|
|
self.suservo.cplds[0].set_att(0, 15.)
|
2022-01-20 16:48:55 +08:00
|
|
|
self.suschannel0.set_y(profile=0, y=0.) # Clear integrator
|
|
|
|
self.suschannel0.set_iir(
|
2022-01-20 16:43:41 +08:00
|
|
|
profile=0,
|
|
|
|
adc=0, # take data from Sampler channel 0
|
|
|
|
kp=-1., # -1 P gain
|
|
|
|
ki=0./s, # no integrator gain
|
|
|
|
g=0., # no integrator gain limit
|
|
|
|
delay=0. # no IIR update delay after enabling
|
|
|
|
)
|
2022-01-20 16:48:55 +08:00
|
|
|
self.suschannel0.set_dds(
|
2022-01-20 16:43:41 +08:00
|
|
|
profile=0,
|
|
|
|
offset=-.3, # 3 V with above PGIA settings
|
|
|
|
frequency=10*MHz,
|
|
|
|
phase=0.)
|
|
|
|
# enable RF, IIR updates and set profile
|
2022-01-20 16:48:55 +08:00
|
|
|
self.suschannel0.set(en_out=1, en_iir=1, profile=0)
|
2022-01-20 16:43:41 +08:00
|
|
|
self.suservo.set_config(enable=1)
|