115 lines
3.8 KiB
Markdown
115 lines
3.8 KiB
Markdown
# Sinara 4410/4412 DDS Urukul (AD9910/AD9912)
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* [Datasheet](https://m-labs.hk/docs/sinara-datasheets/4410-4412.pdf)
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* [Wiki](https://github.com/sinara-hw/Urukul/wiki)
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## JSON
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```json
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{
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"type": "urukul",
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"dds": "<variant>", // ad9910/ad9912
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"ports": [<port num>, <port num>],
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"clk_sel": <clock num>,
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"refclk": <freq>, // for external clock signal
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"pll_en": <0 or 1, default 1> // PLL bypass, to allow higher external clocker frequencies (1e9 for example)
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}
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```
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## Setup
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Check if [SUServo](./suservo.md) is enabled/disabled respective to customer needs. Connect to the clocker source.
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## Testing
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After running `artiq_sinara_test`:
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```text
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*** Testing Urukul DDSes.
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urukul0_cpld: initializing CPLD...
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urukul0_cpld: testing attenuator digital control...
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urukul0_cpld: done
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Calibrating inter-device synchronization...
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urukul0_ch0 no EEPROM synchronization
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urukul0_ch1 no EEPROM synchronization
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urukul0_ch2 no EEPROM synchronization
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urukul0_ch3 no EEPROM synchronization
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...done
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All urukul channels active.
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Check each channel amplitude (~1.6Vpp/8dbm at 50ohm) and frequency.
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Frequencies:
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urukul0_ch0 10MHz
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urukul0_ch1 11MHz
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urukul0_ch2 12MHz
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urukul0_ch3 13MHz
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Press ENTER when done.
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Testing RF switch control. Check LEDs at urukul RF ports.
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Press ENTER when done.
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```
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1. Setup oscilloscope's impedance at 50 ohm
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2. Touch each connector with oscilloscope, setup time- and voltage- scale and trigger, so that you can see sine waves
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3. Measure frequencies and amplitudes on each connector, check with `artiq_sinara_test`'s respective values
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4. When done, proceed with `artiq_sinara_test` and check LEDs are lighting up one after another
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## Common problems
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### Urukul AD9912 product id mismatch
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```pycon
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ValueError: Urukul AD9912 product id mismatch
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```
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Some Urukuls may fail with this error during testing, usually meaning that the Urukul has not been flashed with the
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firmware, especially if the ID is `65535` (you will need to edit the code to check this).
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You can flash the firmware yourself with a JTAG adapter:
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1. Download the latest binary release from [quartiq/urukul](https://github.com/quartiq/urukul) and extract the `urukul.jed` file.
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2. Connect the Urukul with the JTAG adapter to the PC and connect its EEM0 to any available Kasli/Kasli-SoC (do not hot-plug), then turn on the Kasli/Kasli-SoC.
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3. Run `nix-shell -p xc3sprog`.
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4. Run `xc3sprog -c jtaghs2 urukul.jed -m /opt/Xilinx/Vivado/<available version>/data/xicom/cable_data/digilent/lnx64/xbr/`.
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5. If the last command outputs Verify: Success, then your Urukul is ready. It can also output the message
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```shell
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*** buffer overflow detected ***: terminated
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Aborted (core dumped)
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```
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, which is okay if `Verify: Success` was also emitted.
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### no valid window/delay
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```pycon
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ValueError: no valid window/delay
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```
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Check with the customer to see if synchronization is necessary, and disable it if it is not.
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In any case, simply restart the test.
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### Noise instead of signal
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It may be due to misconfiguration of SUServo. Check that both firmware and pins enable/disable the SUServo mode.
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### Improper frequency
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This can happen due to lack/bad clock source connection. Check that clock source is connected respective to the customer needs,
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and if it is connected to the [Clocker](clocker.md), check that clocker receives clock signal properly.
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### Urukul proto_rev mismatch
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```pycon
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ValueError: Urukul proto_rev mismatch
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```
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Check the ports are connected respectively to the JSON description.
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### PLL lock timeout
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```pycon
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ValueError: PLL lock timeout
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```
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This can happen due to lack/bad clock source connection. Check that clock source is connected respective to the customer needs,
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and if it is connected to the [Clocker](clocker.md), check that clocker receives clock signal properly and `EXT`/`INT` pin
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matches real clocker source. |