Syrostan/update_log.txt

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v1.0
-first production version
v1.1
-replace ice40 package with default library BGA256
2021-08-31 17:36:44 +08:00
-optimize buck converter capacitors position
-fix PoE schematic bug
2021-08-31 17:36:44 +08:00
-optimize silk position overlapping
-optimize ENC624J600 decoupling capacitors
-optimize 12V decoupling capacitors
-optimize screw keepout hole
-add external oscillator for FPGA
-fix CPU_IO headers interferes with Analog headers
-fix MCU ADC7 and ADC6 label bug
-1.27mm headers use standard pin numbers (2x12, 2x15, 2x17)
-Connect HSADC clock and FSMC clock to GB pins for better clock performance
v2.0
-Remove 3.3v_MP fuse and add TPS2590 load switch with current control for 3.3v_MP outputs
-change TPS2590 resistor to change current limit to 1A for 12v outputs