59 lines
1.1 KiB
Verilog
59 lines
1.1 KiB
Verilog
module top (
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HW_CLK,
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LED,
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KEY,
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ADC_CLK,
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ADC_DAT,
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FSMC_CLK,
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FSMC_ADD,
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FSMC_DAT,
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FSMC_NL,
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FSMC_NWAIT,
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FSMC_NOE,
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FSMC_NWE,
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FSMC_NBL,
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FSMC_NE1
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);
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/* I/O */
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input HW_CLK;
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input KEY;
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output LED;
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input FSMC_NL;
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input FSMC_NWAIT;
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input FSMC_NOE;
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input FSMC_NWE;
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input FSMC_NE1;
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input [1:0]FSMC_NBL;
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input FSMC_CLK;
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input [7:0]FSMC_ADD;
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output [15:0]FSMC_DAT;
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output ADC_CLK;
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input [7:0]ADC_DAT;
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reg [7:0] adc_result = 8'b0;
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/* Counter register */
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reg [31:0] counter = 32'b0;
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/* LED drivers */
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assign LED = counter[24];
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// assign LED = ~KEY;
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/* always */
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always @ (posedge HW_CLK) begin
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counter <= counter + 1;
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FSMC_DAT = 200;
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ADC_CLK = ~ADC_CLK;
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end
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always @ (posedge ADC_CLK) begin
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adc_result = ADC_DAT;
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// FSMC_DAT = 200;
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end
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endmodule |