69 lines
1.3 KiB
Verilog
69 lines
1.3 KiB
Verilog
/* Machine-generated using Migen */
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module top(
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output eem0_n,
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output eem0_p,
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output eem0_n_1,
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output eem0_p_1,
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inout eem0_n_2,
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output eem0_n_3,
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output eem0_p_2,
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output eem0_n_4,
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output eem0_p_3,
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output eem0_n_5,
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output eem0_p_4,
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output eem0_n_6,
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output eem0_p_5,
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input spi_cs_n,
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output spi_miso,
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input spi_mosi,
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input spi_clk,
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input spi_mosi_1,
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input [2:0] spi_cs,
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output user_led,
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input io_update,
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input clk25
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);
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wire miso_n;
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wire sys_clk;
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wire sys_rst;
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wire por_clk;
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reg int_rst = 1'd1;
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// synthesis translate_off
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reg dummy_s;
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initial dummy_s <= 1'd0;
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// synthesis translate_on
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assign eem0_p = spi_clk; //ch0
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assign eem0_n = (~spi_clk);
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assign eem0_p_1 = spi_mosi_1; //ch1
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assign eem0_n_1 = (~spi_mosi_1);
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assign spi_miso = (~miso_n);
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assign eem0_p_2 = spi_cs[0]; //ch3
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assign eem0_n_3 = (~spi_cs[0]);
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assign eem0_p_3 = spi_cs[1]; //ch4
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assign eem0_n_4 = (~spi_cs[1]);
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assign eem0_p_4 = spi_cs[2]; //ch5
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assign eem0_n_5 = (~spi_cs[2]);
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assign eem0_p_5 = io_update; //ch6
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assign eem0_n_6 = (~io_update);
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assign user_led = 1'd1;
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assign sys_clk = clk25;
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assign por_clk = clk25;
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assign sys_rst = int_rst;
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always @(posedge por_clk) begin
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int_rst <= 1'd0;
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end
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SB_IO #(
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.IO_STANDARD("SB_LVDS_INPUT"),
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.PIN_TYPE(6'd1)
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) SB_IO (
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.PACKAGE_PIN(eem0_n_2),
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.D_IN_0(miso_n)
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);
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endmodule
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