Commit Graph

  • 34042d1c59 add eem0 and eem2 port support; eem0 input working master mikelam 2022-02-04 16:33:41 +0800
  • cf76348432 EEM output working mikelam 2022-01-22 17:50:49 +0800
  • d64ae0e652 add time stamp (in ns) for plotting; ADC working at 80MHz mikelam 2022-01-15 20:52:15 +0800
  • a082a2bd0d use UART to transmit data out and plot wave using python for HSADC performance testing (working well @75MHz) mikelam 2022-01-15 19:38:30 +0800
  • 5d1c7c4d51 FPGA BRAM working mikelam 2022-01-15 15:54:47 +0800
  • 900c0e292f add PLL to generate 50MHz clock for ADC mikelam 2022-01-09 21:28:03 +0800
  • fe0d520b28 use software FSMC to avoid FPGA strange inout issue mikelam 2022-01-09 20:30:28 +0800
  • 32098c89ae multiplexer working mikelam 2021-12-31 10:57:11 +0800
  • 259ec7e7ec HSADC working (under 25MHz clock); FSMC working; make file can generate fpga bitstram as C array mikelam 2021-12-26 16:53:27 +0800
  • a01bf0c0c9 change to STM32F103VFT6; add ADC and SW/LED IO labels; simple testing for 5V GND MOS switch Zheng-Jiakun 2021-08-31 17:38:28 +0800
  • 416bb29b83 add ethernet controller spi driver Zheng-Jiakun 2021-07-27 09:58:57 +0800
  • 71f86fa2ab init project Zheng-Jiakun 2021-07-26 17:17:04 +0800