sinara-hw/Syrostan-MCU-C
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add time stamp (in ns) for plotting; ADC working at 80MHz

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This commit is contained in:
mikelam 2022-01-15 20:52:15 +08:00
parent a082a2bd0d
commit d64ae0e652
4 changed files with 22 additions and 15 deletions
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10
Core/Inc/User/fpga_bin.h
View File

@ -2580,7 +2580,7 @@ const unsigned char __build_syrostan_fpga_bin[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@ -2589,7 +2589,7 @@ const unsigned char __build_syrostan_fpga_bin[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x04, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x04, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@ -2598,7 +2598,7 @@ const unsigned char __build_syrostan_fpga_bin[] = {
0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x02, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x02, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
@ -11256,7 +11256,7 @@ const unsigned char __build_syrostan_fpga_bin[] = {
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0xa1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x6f,
0x33, 0x01, 0x06, 0x00 0xf8, 0x01, 0x06, 0x00
}; };
unsigned int __build_syrostan_fpga_bin_len = 135100; unsigned int __build_syrostan_fpga_bin_len = 135100;

3
Core/Src/User/user_main.c
View File

@ -14,6 +14,9 @@ void user_setup()
eem_power_init(); eem_power_init();
uint8_t str[10] = "start"; uint8_t str[10] = "start";
HAL_UART_Transmit(&huart4, str, 6, 100); HAL_UART_Transmit(&huart4, str, 6, 100);
HAL_GPIO_WritePin(GND1_SW_GPIO_Port, GND1_SW_Pin, GPIO_PIN_SET);
HAL_GPIO_WritePin(GND2_SW_GPIO_Port, GND2_SW_Pin, GPIO_PIN_SET);
} }
uint8_t dio_ch = 0; uint8_t dio_ch = 0;

12
FPGA/top.v
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@ -32,17 +32,17 @@ module top (
counter <= counter + 1; counter <= counter + 1;
end end
wire CLK_50M; wire CLK_80M;
SB_PLL40_CORE #(.FEEDBACK_PATH("SIMPLE"), SB_PLL40_CORE #(.FEEDBACK_PATH("SIMPLE"),
.PLLOUT_SELECT("GENCLK"), .PLLOUT_SELECT("GENCLK"),
.DIVR(4'd0), .DIVR(4'd4),
.DIVF(7'd2), .DIVF(7'd15),
.DIVQ(3'd0), //12MHz * (DIVF+1) / 2^DIVQ / (DIVR+1) .DIVQ(3'd0), //25MHz * (DIVF+1) / 2^DIVQ / (DIVR+1)
.FILTER_RANGE(3'b001), // wfm without PLL is broken .FILTER_RANGE(3'b001), // wfm without PLL is broken
) uut ( ) uut (
.REFERENCECLK(CLK_25M), .REFERENCECLK(CLK_25M),
.PLLOUTCORE(CLK_50M), .PLLOUTCORE(CLK_80M),
// .LOCK(P16), // .LOCK(P16),
.RESETB(1'b1), .RESETB(1'b1),
.BYPASS(1'b0) .BYPASS(1'b0)
@ -50,7 +50,7 @@ module top (
parameter ADC_RAM_DEPTH = 16384; parameter ADC_RAM_DEPTH = 16384;
/* high-speed ADC */ /* high-speed ADC */
assign ADC_CLK = CLK_50M; assign ADC_CLK = CLK_80M;
reg [7:0] adc_buf = 8'b0; reg [7:0] adc_buf = 8'b0;
reg [7:0] adc_ram [0:ADC_RAM_DEPTH-1]; reg [7:0] adc_ram [0:ADC_RAM_DEPTH-1];
reg [15:0] ram_pointer = 0; reg [15:0] ram_pointer = 0;

12
plot_adc.py
View File

@ -1,14 +1,18 @@
length = 16384 length = 16384
ADC_PERIOD = 12.5 # ns
import serial import serial
import numpy as np import numpy as np
import matplotlib.pyplot as plt import matplotlib.pyplot as plt
ser = serial.Serial('/dev/ttyUSB0', 115200, timeout=None) ser = serial.Serial('/dev/ttyUSB0', 115200, timeout=None)
# print(ser.name) # check which port was really used
buffer = ser.read(length); buffer = ser.read(length);
data = [] x = [float(x)*ADC_PERIOD for x in range(length)]
# print(x)
y = []
for i in range(length): for i in range(length):
data.append(np.int8(buffer[i])) y.append(np.int8(buffer[i]))
# print(data) # print(y)
plt.plot(data) plt.plot(x, y)
plt.show() plt.show()
ser.close() ser.close()