From d64ae0e65248b02de9627c6d9d93b6ad263fcc9a Mon Sep 17 00:00:00 2001
From: mikelam <mikelam@m-labs.hk>
Date: Sat, 15 Jan 2022 20:52:15 +0800
Subject: [PATCH] add time stamp (in ns) for plotting; ADC working at 80MHz

---
 Core/Inc/User/fpga_bin.h  | 10 +++++-----
 Core/Src/User/user_main.c |  3 +++
 FPGA/top.v                | 12 ++++++------
 plot_adc.py               | 12 ++++++++----
 4 files changed, 22 insertions(+), 15 deletions(-)

diff --git a/Core/Inc/User/fpga_bin.h b/Core/Inc/User/fpga_bin.h
index ec63237..1355dc5 100644
--- a/Core/Inc/User/fpga_bin.h
+++ b/Core/Inc/User/fpga_bin.h
@@ -2580,7 +2580,7 @@ const unsigned char __build_syrostan_fpga_bin[] = {
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2589,7 +2589,7 @@ const unsigned char __build_syrostan_fpga_bin[] = {
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x04, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
@@ -2598,7 +2598,7 @@ const unsigned char __build_syrostan_fpga_bin[] = {
   0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x0c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x02, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00,
@@ -11256,7 +11256,7 @@ const unsigned char __build_syrostan_fpga_bin[] = {
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0xa1,
-  0x33, 0x01, 0x06, 0x00
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x22, 0x6f,
+  0xf8, 0x01, 0x06, 0x00
 };
 unsigned int __build_syrostan_fpga_bin_len = 135100;
diff --git a/Core/Src/User/user_main.c b/Core/Src/User/user_main.c
index c7b40d3..ba8a200 100644
--- a/Core/Src/User/user_main.c
+++ b/Core/Src/User/user_main.c
@@ -14,6 +14,9 @@ void user_setup()
     eem_power_init();
     uint8_t str[10] = "start";
     HAL_UART_Transmit(&huart4, str, 6, 100);
+
+    HAL_GPIO_WritePin(GND1_SW_GPIO_Port, GND1_SW_Pin, GPIO_PIN_SET);
+    HAL_GPIO_WritePin(GND2_SW_GPIO_Port, GND2_SW_Pin, GPIO_PIN_SET);
 }
 
 uint8_t dio_ch = 0;
diff --git a/FPGA/top.v b/FPGA/top.v
index 0b93a9e..86c6bcd 100644
--- a/FPGA/top.v
+++ b/FPGA/top.v
@@ -32,17 +32,17 @@ module top (
         counter <= counter + 1;
     end
 
-    wire CLK_50M;
+    wire CLK_80M;
     SB_PLL40_CORE #(.FEEDBACK_PATH("SIMPLE"),
                     .PLLOUT_SELECT("GENCLK"),
-                    .DIVR(4'd0),
-                    .DIVF(7'd2),  
-                    .DIVQ(3'd0),  //12MHz * (DIVF+1) / 2^DIVQ / (DIVR+1)
+                    .DIVR(4'd4),
+                    .DIVF(7'd15),
+                    .DIVQ(3'd0),  //25MHz * (DIVF+1) / 2^DIVQ / (DIVR+1)
 
                     .FILTER_RANGE(3'b001),  // wfm without PLL is broken
                     ) uut (
                             .REFERENCECLK(CLK_25M),
-                            .PLLOUTCORE(CLK_50M),
+                            .PLLOUTCORE(CLK_80M),
     //                        .LOCK(P16),
                             .RESETB(1'b1),
                             .BYPASS(1'b0)
@@ -50,7 +50,7 @@ module top (
 
     parameter ADC_RAM_DEPTH = 16384;
 /* high-speed ADC */
-    assign ADC_CLK = CLK_50M;
+    assign ADC_CLK = CLK_80M;
     reg [7:0] adc_buf = 8'b0;
     reg [7:0] adc_ram [0:ADC_RAM_DEPTH-1];
     reg [15:0] ram_pointer = 0;
diff --git a/plot_adc.py b/plot_adc.py
index c4c2568..381c12a 100644
--- a/plot_adc.py
+++ b/plot_adc.py
@@ -1,14 +1,18 @@
 length = 16384
+ADC_PERIOD = 12.5 # ns
 
 import serial
 import numpy as np
 import matplotlib.pyplot as plt
 ser = serial.Serial('/dev/ttyUSB0', 115200, timeout=None)
+# print(ser.name)         # check which port was really used
 buffer = ser.read(length);
-data = []
+x = [float(x)*ADC_PERIOD for x in range(length)]
+# print(x)
+y = []
 for i in range(length):
-    data.append(np.int8(buffer[i]))
-# print(data)
-plt.plot(data)
+    y.append(np.int8(buffer[i]))
+# print(y)
+plt.plot(x, y)
 plt.show()
 ser.close()
\ No newline at end of file