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EEM output working

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This commit is contained in:
mikelam 2022-01-22 17:50:49 +08:00
parent d64ae0e652
commit cf76348432
18 changed files with 35066 additions and 7406 deletions
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3
.vscode/settings.json vendored
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@ -11,6 +11,7 @@
"stdlib.h": "c",
"gpio.h": "c",
"stm32f1xx_hal.h": "c",
"stm32f1xx_hal_conf.h": "c"
"stm32f1xx_hal_conf.h": "c",
"test_logic.h": "c"
}
}

14662
Core/Inc/User/fpga_bin.h
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1
Core/Inc/User/test_logic.h
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@ -3,6 +3,7 @@
#include "user_main.h"
void hsadc();
void key_events();
#endif

50
Core/Src/User/test_logic.c
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@ -1,5 +1,40 @@
#include "test_logic.h"
#define ADC_SAMPLE_NUM 16384
uint8_t fsmc_read_buf, fsmc_write_buf;
int8_t adc_result[ADC_SAMPLE_NUM];
uint8_t dio_ch = 1;
uint8_t dio_io = 0;
uint8_t adc_sample = 0;
uint16_t fsmc_add = 0;
void hsadc()
{
if (adc_sample)
{
adc_sample = 0;
fsmc_write_buf = (dio_io & 0x01) | ((dio_ch & 0x07) << 1) | 0x10;
fsmc_write(fsmc_write_buf, 0);
}
// fsmc_read(0xffff, (uint8_t*)&fsmc_read_buf);
// if (fsmc_read_buf & 0x02)
if (HAL_GPIO_ReadPin(FSMC_NWAIT_GPIO_Port, FSMC_NWAIT_Pin) == GPIO_PIN_SET)
{
fsmc_write_buf = (dio_io & 0x01) | ((dio_ch & 0x07) << 1);
fsmc_write(fsmc_write_buf, 0);
fsmc_add = 0;
while (fsmc_add < ADC_SAMPLE_NUM)
{
fsmc_read(fsmc_add, (uint8_t*)(adc_result + fsmc_add));
fsmc_add++;
}
// HAL_UART_Transmit(&huart4, "test0", 6, 100);
HAL_UART_Transmit(&huart4, (uint8_t*)adc_result, ADC_SAMPLE_NUM, 10000);
}
}
void key_events()
{
//button on board
@ -10,6 +45,7 @@ void key_events()
{
// ethernet_spi_1_byte(ENC_CMD_RESET);
// ethernet_reset();
adc_sample = 1;
while (HAL_GPIO_ReadPin(KEY_GPIO_Port, KEY_Pin) == GPIO_PIN_RESET);
}
}
@ -24,7 +60,7 @@ void key_events()
eem_power_off();
}
//small buttons 1 (turn on GND1 MOS)
//small buttons 1 (toggle GND1 MOS)
if (HAL_GPIO_ReadPin(SW5_GPIO_Port, SW5_Pin) == GPIO_PIN_RESET)
{
HAL_Delay(50);
@ -35,7 +71,7 @@ void key_events()
}
}
//small buttons 2 (turn on GND2 MOS)
//small buttons 2 (toggle GND2 MOS)
if (HAL_GPIO_ReadPin(SW4_GPIO_Port, SW4_Pin) == GPIO_PIN_RESET)
{
HAL_Delay(50);
@ -52,14 +88,10 @@ void key_events()
HAL_Delay(50);
if (HAL_GPIO_ReadPin(SW3_GPIO_Port, SW3_Pin) == GPIO_PIN_RESET)
{
HAL_GPIO_WritePin(GND1_SW_GPIO_Port, GND1_SW_Pin, GPIO_PIN_RESET);
HAL_GPIO_WritePin(GND2_SW_GPIO_Port, GND2_SW_Pin, GPIO_PIN_RESET);
adc_sample = 1;
// HAL_GPIO_WritePin(GND1_SW_GPIO_Port, GND1_SW_Pin, GPIO_PIN_RESET);
// HAL_GPIO_WritePin(GND2_SW_GPIO_Port, GND2_SW_Pin, GPIO_PIN_RESET);
while (HAL_GPIO_ReadPin(SW3_GPIO_Port, SW3_Pin) == GPIO_PIN_RESET);
}
}
}
void DUT_on()
{
eem_power_on();
}

43
Core/Src/User/user_main.c
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@ -1,10 +1,5 @@
#include "user_main.h"
#define ADC_SAMPLE_NUM 16384
uint8_t fsmc_read_buf, fsmc_write_buf;
int8_t adc_result[ADC_SAMPLE_NUM];
void user_setup()
{
flash_fpga();
@ -19,42 +14,8 @@ void user_setup()
HAL_GPIO_WritePin(GND2_SW_GPIO_Port, GND2_SW_Pin, GPIO_PIN_SET);
}
uint8_t dio_ch = 0;
uint8_t dio_io = 0;
uint8_t adc_sample = 0;
uint16_t fsmc_add = 0;
void user_loop()
{
if (adc_sample)
{
adc_sample = 0;
fsmc_write_buf = (dio_io & 0x01) | ((dio_ch & 0x03) << 1) | 0x10;
fsmc_write(fsmc_write_buf, 0);
}
// fsmc_read(0xffff, (uint8_t*)&fsmc_read_buf);
// if (fsmc_read_buf & 0x02)
if (HAL_GPIO_ReadPin(FSMC_NWAIT_GPIO_Port, FSMC_NWAIT_Pin) == GPIO_PIN_SET)
{
fsmc_write_buf = (dio_io & 0x01) | ((dio_ch & 0x03) << 1);
fsmc_write(fsmc_write_buf, 0);
fsmc_add = 0;
while (fsmc_add < ADC_SAMPLE_NUM)
{
fsmc_read(fsmc_add, (uint8_t*)(adc_result + fsmc_add));
fsmc_add++;
}
// HAL_UART_Transmit(&huart4, "test0", 6, 100);
HAL_UART_Transmit(&huart4, (uint8_t*)adc_result, ADC_SAMPLE_NUM, 10000);
}
// HAL_Delay(1000);
// key_events();
if (HAL_GPIO_ReadPin(KEY_GPIO_Port, KEY_Pin) == GPIO_PIN_RESET)
{
HAL_Delay(50);
if (HAL_GPIO_ReadPin(KEY_GPIO_Port, KEY_Pin) == GPIO_PIN_RESET)
{
adc_sample = 1;
while (HAL_GPIO_ReadPin(KEY_GPIO_Port, KEY_Pin) == GPIO_PIN_RESET);
}
}
hsadc();
key_events();
}

0
FPGA/lvds.py → FPGA/lvds/lvds.py
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BIN
FPGA/lvds/top.bin Normal file
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Binary file not shown.

5989
FPGA/lvds/top.json Normal file
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File diff suppressed because it is too large Load Diff

24
FPGA/lvds/top.pcf Normal file
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@ -0,0 +1,24 @@
set_io eem0_n H1
set_io eem0_p J3
set_io eem0_n_1 B1
set_io eem0_p_1 F5
set_io eem0_n_2 C2
set_io eem0_n_3 D2
set_io eem0_p_2 F4 //p3
set_io eem0_n_4 D1
set_io eem0_p_3 G5 //p4
set_io eem0_n_5 E3
set_io eem0_p_4 G4 //p5
set_io eem0_n_6 E2
set_io eem0_p_5 H5 //p6
set_io spi_cs_n R2
set_io spi_miso T2
set_io spi_mosi N5
set_io spi_clk C8
set_io spi_mosi_1 B16
set_io spi_cs[0] B13
set_io spi_cs[1] B14
set_io spi_cs[2] B15
set_io user_led H3
set_io io_update A11
set_io clk25 K9

641
FPGA/lvds/top.rpt Normal file
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@ -0,0 +1,641 @@
/----------------------------------------------------------------------------\
| |
| yosys -- Yosys Open SYnthesis Suite |
| |
| Copyright (C) 2012 - 2019 Clifford Wolf <clifford@clifford.at> |
| |
| Permission to use, copy, modify, and/or distribute this software for any |
| purpose with or without fee is hereby granted, provided that the above |
| copyright notice and this permission notice appear in all copies. |
| |
| THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| |
\----------------------------------------------------------------------------/
Yosys 0.9 (git sha1 1979e0b)
-- Executing script file `top.ys' --
1. Executing Verilog-2005 frontend: top.v
Parsing Verilog input from `top.v' to AST representation.
Warning: Found one of those horrible `(synopsys|synthesis) translate_off' comments.
Yosys does support them but it is recommended to use `ifdef constructs instead!
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.
2. Executing ATTRMAP pass (move or copy attributes).
3. Executing SYNTH_ICE40 pass.
3.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\SB_IO'.
Generating RTLIL representation for module `\SB_GB_IO'.
Generating RTLIL representation for module `\SB_GB'.
Generating RTLIL representation for module `\SB_LUT4'.
Generating RTLIL representation for module `\SB_CARRY'.
Generating RTLIL representation for module `\SB_DFF'.
Generating RTLIL representation for module `\SB_DFFE'.
Generating RTLIL representation for module `\SB_DFFSR'.
Generating RTLIL representation for module `\SB_DFFR'.
Generating RTLIL representation for module `\SB_DFFSS'.
Generating RTLIL representation for module `\SB_DFFS'.
Generating RTLIL representation for module `\SB_DFFESR'.
Generating RTLIL representation for module `\SB_DFFER'.
Generating RTLIL representation for module `\SB_DFFESS'.
Generating RTLIL representation for module `\SB_DFFES'.
Generating RTLIL representation for module `\SB_DFFN'.
Generating RTLIL representation for module `\SB_DFFNE'.
Generating RTLIL representation for module `\SB_DFFNSR'.
Generating RTLIL representation for module `\SB_DFFNR'.
Generating RTLIL representation for module `\SB_DFFNSS'.
Generating RTLIL representation for module `\SB_DFFNS'.
Generating RTLIL representation for module `\SB_DFFNESR'.
Generating RTLIL representation for module `\SB_DFFNER'.
Generating RTLIL representation for module `\SB_DFFNESS'.
Generating RTLIL representation for module `\SB_DFFNES'.
Generating RTLIL representation for module `\SB_RAM40_4K'.
Generating RTLIL representation for module `\SB_RAM40_4KNR'.
Generating RTLIL representation for module `\SB_RAM40_4KNW'.
Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
Generating RTLIL representation for module `\ICESTORM_LC'.
Generating RTLIL representation for module `\SB_PLL40_CORE'.
Generating RTLIL representation for module `\SB_PLL40_PAD'.
Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
Generating RTLIL representation for module `\SB_WARMBOOT'.
Generating RTLIL representation for module `\SB_SPRAM256KA'.
Generating RTLIL representation for module `\SB_HFOSC'.
Generating RTLIL representation for module `\SB_LFOSC'.
Generating RTLIL representation for module `\SB_RGBA_DRV'.
Generating RTLIL representation for module `\SB_LED_DRV_CUR'.
Generating RTLIL representation for module `\SB_RGB_DRV'.
Generating RTLIL representation for module `\SB_I2C'.
Generating RTLIL representation for module `\SB_SPI'.
Generating RTLIL representation for module `\SB_LEDDA_IP'.
Generating RTLIL representation for module `\SB_FILTER_50NS'.
Generating RTLIL representation for module `\SB_IO_I3C'.
Generating RTLIL representation for module `\SB_IO_OD'.
Generating RTLIL representation for module `\SB_MAC16'.
Successfully finished Verilog frontend.
3.2. Executing HIERARCHY pass (managing design hierarchy).
3.2.1. Analyzing design hierarchy..
Top module: \top
3.2.2. Analyzing design hierarchy..
Top module: \top
Removed 0 unused modules.
3.3. Executing PROC pass (convert processes to netlists).
3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.
3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.
3.3.3. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\top.$proc$top.v:31$9'.
Set init value: \int_rst = 1'1
3.3.4. Executing PROC_ARST pass (detect async resets in processes).
3.3.5. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\top.$proc$top.v:31$9'.
1/1: $1\int_rst[0:0]
Creating decoders for process `\top.$proc$top.v:56$8'.
1/1: $0\int_rst[0:0]
3.3.6. Executing PROC_DLATCH pass (convert process syncs to latches).
3.3.7. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\top.\int_rst' using process `\top.$proc$top.v:56$8'.
created $dff cell `$procdff$10' with positive edge clock.
3.3.8. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `top.$proc$top.v:31$9'.
Removing empty process `top.$proc$top.v:56$8'.
Cleaned up 0 empty switches.
3.4. Executing FLATTEN pass (flatten design).
No more expansions possible.
3.5. Executing TRIBUF pass.
3.6. Executing DEMINOUT pass (demote inout ports to input or output).
3.7. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 9 unused wires.
<suppressed ~2 debug messages>
3.9. Executing CHECK pass (checking for obvious problems).
checking module top..
found and reported 0 problems.
3.10. Executing OPT pass (performing simple optimizations).
3.10.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.10.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
3.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
3.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
3.10.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
3.10.6. Executing OPT_RMDFF pass (remove dff with constant values).
Promoting init spec \int_rst = 1'1 to constant driver in module top.
Promoted 1 init specs to constant drivers.
3.10.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
3.10.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.10.9. Rerunning OPT passes. (Maybe there is more to do..)
3.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
3.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
3.10.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
3.10.13. Executing OPT_RMDFF pass (remove dff with constant values).
3.10.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
3.10.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.10.16. Finished OPT passes. (There is nothing left to do.)
3.11. Executing WREDUCE pass (reducing word size of cells).
3.12. Executing PEEPOPT pass (run peephole optimizers).
3.13. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
3.14. Executing SHARE pass (SAT-based resource sharing).
3.15. Executing TECHMAP pass (map to technology primitives).
3.15.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v
Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.
3.15.2. Continuing TECHMAP pass.
No more expansions possible.
3.16. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
3.18. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
created 0 $alu and 0 $macc cells.
3.19. Executing OPT pass (performing simple optimizations).
3.19.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.19.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
3.19.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
3.19.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
3.19.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
3.19.6. Executing OPT_RMDFF pass (remove dff with constant values).
3.19.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
3.19.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.19.9. Finished OPT passes. (There is nothing left to do.)
3.20. Executing FSM pass (extract and optimize FSM).
3.20.1. Executing FSM_DETECT pass (finding FSMs in design).
3.20.2. Executing FSM_EXTRACT pass (extracting FSM from design).
3.20.3. Executing FSM_OPT pass (simple optimizations of FSMs).
3.20.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
3.20.5. Executing FSM_OPT pass (simple optimizations of FSMs).
3.20.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
3.20.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
3.20.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
3.21. Executing OPT pass (performing simple optimizations).
3.21.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.21.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
3.21.3. Executing OPT_RMDFF pass (remove dff with constant values).
3.21.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
3.21.5. Finished fast OPT passes.
3.22. Executing MEMORY pass.
3.22.1. Executing MEMORY_DFF pass (merging $dff cells to $memrd and $memwr).
3.22.2. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
3.22.3. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
3.22.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
3.22.5. Executing MEMORY_COLLECT pass (generating $mem cells).
3.23. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
3.24. Executing MEMORY_BRAM pass (mapping $mem cells to block memories).
3.25. Executing TECHMAP pass (map to technology primitives).
3.25.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ICE40_RAM4K'.
Generating RTLIL representation for module `\$__ICE40_RAM4K_M0'.
Generating RTLIL representation for module `\$__ICE40_RAM4K_M123'.
Successfully finished Verilog frontend.
3.25.2. Continuing TECHMAP pass.
No more expansions possible.
3.26. Executing ICE40_BRAMINIT pass.
3.27. Executing OPT pass (performing simple optimizations).
3.27.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.27.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
3.27.3. Executing OPT_RMDFF pass (remove dff with constant values).
3.27.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
3.27.5. Finished fast OPT passes.
3.28. Executing MEMORY_MAP pass (converting $mem cells to logic and flip-flops).
3.29. Executing OPT pass (performing simple optimizations).
3.29.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.29.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
3.29.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
Creating internal representation of mux trees.
No muxes found in this module.
Removed 0 multiplexer ports.
3.29.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
Optimizing cells in module \top.
Performed a total of 0 changes.
3.29.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
3.29.6. Executing OPT_RMDFF pass (remove dff with constant values).
3.29.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
3.29.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.29.9. Finished OPT passes. (There is nothing left to do.)
3.30. Executing TECHMAP pass (map to technology primitives).
3.30.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.
3.30.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ice40_alu'.
Successfully finished Verilog frontend.
3.30.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $not.
No more expansions possible.
<suppressed ~7 debug messages>
3.31. Executing ICE40_OPT pass (performing simple optimizations).
3.31.1. Running ICE40 specific optimizations.
3.31.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.31.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
3.31.4. Executing OPT_RMDFF pass (remove dff with constant values).
3.31.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
3.31.6. Finished OPT passes. (There is nothing left to do.)
3.32. Executing DFFSR2DFF pass (mapping DFFSR cells to simpler FFs).
3.33. Executing DFF2DFFE pass (transform $dff to $dffe where applicable).
Selected cell types for direct conversion:
$_DFF_PP1_ -> $__DFFE_PP1
$_DFF_PP0_ -> $__DFFE_PP0
$_DFF_PN1_ -> $__DFFE_PN1
$_DFF_PN0_ -> $__DFFE_PN0
$_DFF_NP1_ -> $__DFFE_NP1
$_DFF_NP0_ -> $__DFFE_NP0
$_DFF_NN1_ -> $__DFFE_NN1
$_DFF_NN0_ -> $__DFFE_NN0
$_DFF_N_ -> $_DFFE_NP_
$_DFF_P_ -> $_DFFE_PP_
Transforming FF to FF+Enable cells in module top:
3.34. Executing TECHMAP pass (map to technology primitives).
3.34.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NN0_'.
Generating RTLIL representation for module `\$_DFF_NN1_'.
Generating RTLIL representation for module `\$_DFF_PN0_'.
Generating RTLIL representation for module `\$_DFF_PN1_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$__DFFE_NN0'.
Generating RTLIL representation for module `\$__DFFE_NN1'.
Generating RTLIL representation for module `\$__DFFE_PN0'.
Generating RTLIL representation for module `\$__DFFE_PN1'.
Generating RTLIL representation for module `\$__DFFE_NP0'.
Generating RTLIL representation for module `\$__DFFE_NP1'.
Generating RTLIL representation for module `\$__DFFE_PP0'.
Generating RTLIL representation for module `\$__DFFE_PP1'.
Successfully finished Verilog frontend.
3.34.2. Continuing TECHMAP pass.
No more expansions possible.
3.35. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.36. Executing SIMPLEMAP pass (map simple cells to gate primitives).
3.37. Executing ICE40_FFINIT pass (implement FF init values).
Handling FF init values in top.
3.38. Executing ICE40_FFSSR pass (merge synchronous set/reset into FF cells).
Merging set/reset $_MUX_ cells into SB_FFs in top.
3.39. Executing ICE40_OPT pass (performing simple optimizations).
3.39.1. Running ICE40 specific optimizations.
3.39.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
3.39.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.
3.39.4. Executing OPT_RMDFF pass (remove dff with constant values).
3.39.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
3.39.6. Finished OPT passes. (There is nothing left to do.)
3.40. Executing TECHMAP pass (map to technology primitives).
3.40.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.
3.40.2. Continuing TECHMAP pass.
No more expansions possible.
3.41. Executing ABC pass (technology mapping using ABC).
3.41.1. Extracting gate netlist of module `\top' to `<abc-temp-dir>/input.blif'..
Extracted 7 gates and 14 wires to a netlist network with 7 inputs and 7 outputs.
3.41.1.1. Executing ABC.
Running ABC command: berkeley-abc -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC:
ABC: + read_blif <abc-temp-dir>/input.blif
ABC: + read_lut <abc-temp-dir>/lutdefs.txt
ABC: + strash
ABC: + ifraig
ABC: + scorr
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2
ABC: + dretime
ABC: + retime
ABC: + strash
ABC: + dch -f
ABC: + if
ABC: + mfs2
ABC: + lutpack -S 1
ABC: + dress
ABC: Total number of equiv classes = 8.
ABC: Participating nodes from both networks = 14.
ABC: Participating nodes from the first network = 7. ( 87.50 % of nodes)
ABC: Participating nodes from the second network = 7. ( 87.50 % of nodes)
ABC: Node pairs (any polarity) = 7. ( 87.50 % of names can be moved)
ABC: Node pairs (same polarity) = 7. ( 87.50 % of names can be moved)
ABC: Total runtime = 0.00 sec
ABC: + write_blif <abc-temp-dir>/output.blif
3.41.1.2. Re-integrating ABC results.
ABC RESULTS: $lut cells: 14
ABC RESULTS: internal signals: 0
ABC RESULTS: input signals: 7
ABC RESULTS: output signals: 7
Removing temp directory.
Removed 0 unused cells and 14 unused wires.
3.42. Executing TECHMAP pass (map to technology primitives).
3.42.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NN_'.
Generating RTLIL representation for module `\$_DFFE_PN_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NN0_'.
Generating RTLIL representation for module `\$_DFF_NN1_'.
Generating RTLIL representation for module `\$_DFF_PN0_'.
Generating RTLIL representation for module `\$_DFF_PN1_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$__DFFE_NN0'.
Generating RTLIL representation for module `\$__DFFE_NN1'.
Generating RTLIL representation for module `\$__DFFE_PN0'.
Generating RTLIL representation for module `\$__DFFE_PN1'.
Generating RTLIL representation for module `\$__DFFE_NP0'.
Generating RTLIL representation for module `\$__DFFE_NP1'.
Generating RTLIL representation for module `\$__DFFE_PP0'.
Generating RTLIL representation for module `\$__DFFE_PP1'.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.
3.42.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=1\LUT=2'01 for cells of type $lut.
No more expansions possible.
<suppressed ~18 debug messages>
Removed 0 unused cells and 14 unused wires.
3.43. Executing HIERARCHY pass (managing design hierarchy).
3.43.1. Analyzing design hierarchy..
Top module: \top
3.43.2. Analyzing design hierarchy..
Top module: \top
Removed 0 unused modules.
3.44. Printing statistics.
=== top ===
Number of wires: 27
Number of wire bits: 29
Number of public wires: 27
Number of public wire bits: 29
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 8
SB_IO 1
SB_LUT4 7
3.45. Executing CHECK pass (checking for obvious problems).
checking module top..
found and reported 0 problems.
3.46. Executing JSON backend.
Warnings: 1 unique messages, 1 total
End of script. Logfile hash: f800107203
CPU: user 0.26s system 0.01s, MEM: 30.72 MB total, 25.27 MB resident
Yosys 0.9 (git sha1 1979e0b)
Time spent: 51% 11x read_verilog (0 sec), 15% 1x share (0 sec), ...

20853
FPGA/lvds/top.txt Normal file
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File diff suppressed because it is too large Load Diff

68
FPGA/lvds/top.v Normal file
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@ -0,0 +1,68 @@
/* Machine-generated using Migen */
module top(
output eem0_n,
output eem0_p,
output eem0_n_1,
output eem0_p_1,
inout eem0_n_2,
output eem0_n_3,
output eem0_p_2,
output eem0_n_4,
output eem0_p_3,
output eem0_n_5,
output eem0_p_4,
output eem0_n_6,
output eem0_p_5,
input spi_cs_n,
output spi_miso,
input spi_mosi,
input spi_clk,
input spi_mosi_1,
input [2:0] spi_cs,
output user_led,
input io_update,
input clk25
);
wire miso_n;
wire sys_clk;
wire sys_rst;
wire por_clk;
reg int_rst = 1'd1;
// synthesis translate_off
reg dummy_s;
initial dummy_s <= 1'd0;
// synthesis translate_on
assign eem0_p = spi_clk; //ch0
assign eem0_n = (~spi_clk);
assign eem0_p_1 = spi_mosi_1; //ch1
assign eem0_n_1 = (~spi_mosi_1);
assign spi_miso = (~miso_n);
assign eem0_p_2 = spi_cs[0]; //ch3
assign eem0_n_3 = (~spi_cs[0]);
assign eem0_p_3 = spi_cs[1]; //ch4
assign eem0_n_4 = (~spi_cs[1]);
assign eem0_p_4 = spi_cs[2]; //ch5
assign eem0_n_5 = (~spi_cs[2]);
assign eem0_p_5 = io_update; //ch6
assign eem0_n_6 = (~io_update);
assign user_led = 1'd1;
assign sys_clk = clk25;
assign por_clk = clk25;
assign sys_rst = int_rst;
always @(posedge por_clk) begin
int_rst <= 1'd0;
end
SB_IO #(
.IO_STANDARD("SB_LVDS_INPUT"),
.PIN_TYPE(6'd1)
) SB_IO (
.PACKAGE_PIN(eem0_n_2),
.D_IN_0(miso_n)
);
endmodule

3
FPGA/lvds/top.ys Normal file
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@ -0,0 +1,3 @@
read_verilog top.v
attrmap -tocase keep -imap keep="true" keep=1 -imap keep="false" keep=0 -remove keep=0
synth_ice40 -top top -json top.json

1
FPGA/lvds/top_pre_pack.py Normal file
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@ -0,0 +1 @@
ctx.addClock("clk25", 25.0)

19
FPGA/pinmap.pcf
View File

@ -75,3 +75,22 @@ set_io --warn-no-port FSMC_NBL[1] C12
set_io --warn-no-port FSMC_CLK B13
set_io --warn-no-port FSMC_NE1 A16
set_io --warn-no-port eem1_n_0 M5
set_io --warn-no-port eem1_p_0 P2
set_io --warn-no-port eem1_n_1 M4
set_io --warn-no-port eem1_p_1 P1
set_io --warn-no-port eem1_n_2 M2
set_io --warn-no-port eem1_p_2 K5
set_io --warn-no-port eem1_n_3 M1
set_io --warn-no-port eem1_p_3 K4
set_io --warn-no-port eem1_n_4 K3
set_io --warn-no-port eem1_p_4 K1
set_io --warn-no-port eem1_n_5 J1
set_io --warn-no-port eem1_p_5 J2
set_io --warn-no-port eem1_n_6 H1
set_io --warn-no-port eem1_p_6 J3
set_io --warn-no-port eem1_n_7 G1
set_io --warn-no-port eem1_p_7 J5

90
FPGA/top.v
View File

@ -10,8 +10,8 @@ module top (
input [15:0]FSMC_ADD,
inout [7:0]FSMC_DAT,
input [1:0]FSMC_NBL,
inout FSMC_CLK,
inout FSMC_NWAIT,
output FSMC_CLK,
output FSMC_NWAIT,
output ADC_CLK,
input [7:0]ADC_DAT,
@ -19,19 +19,36 @@ module top (
output DIO_OUT,
output DIO_IO_SEL,
output [2:0]DIO_CH_SEL,
output eem1_n_0,
output eem1_p_0,
output eem1_n_1,
output eem1_p_1,
inout eem1_n_2,
output eem1_p_2,
output eem1_n_3,
output eem1_p_3,
output eem1_n_4,
output eem1_p_4,
output eem1_n_5,
output eem1_p_5,
output eem1_n_6,
output eem1_p_6,
output eem1_n_7,
output eem1_p_7,
);
/* Counter register */
/* LED */
reg [31:0] counter = 32'b0;
/* LED drivers */
// assign LED = counter[24];
assign LED = counter[24];
// assign LED = ~KEY;
/* always */
always @ (posedge CLK_25M) begin
counter <= counter + 1;
end
/* high-speed ADC */
wire CLK_80M;
SB_PLL40_CORE #(.FEEDBACK_PATH("SIMPLE"),
.PLLOUT_SELECT("GENCLK"),
@ -41,15 +58,15 @@ module top (
.FILTER_RANGE(3'b001), // wfm without PLL is broken
) uut (
.REFERENCECLK(CLK_25M),
.PLLOUTCORE(CLK_80M),
// .LOCK(P16),
.RESETB(1'b1),
.BYPASS(1'b0)
);
.REFERENCECLK(CLK_25M),
.PLLOUTCORE(CLK_80M),
// .LOCK(P16),
.RESETB(1'b1),
.BYPASS(1'b0)
);
parameter ADC_RAM_DEPTH = 16384;
/* high-speed ADC */
assign ADC_CLK = CLK_80M;
reg [7:0] adc_buf = 8'b0;
reg [7:0] adc_ram [0:ADC_RAM_DEPTH-1];
@ -95,6 +112,51 @@ module top (
// assign FSMC_DAT = FSMC_RE ? fsmc_buf : 8'hzz;
// assign FSMC_CLK = adc_status[0];
assign FSMC_NWAIT = adc_status[1];
assign LED = adc_status[1];
/* LVDS */
wire eem_ch0;
wire eem_ch1;
wire eem_ch2;
wire eem_ch3;
wire eem_ch4;
wire eem_ch5;
wire eem_ch6;
wire eem_ch7;
assign eem1_n_0 = eem_ch0;
assign eem1_p_0 = ~eem_ch0;
assign eem1_n_1 = eem_ch1;
assign eem1_p_1 = ~eem_ch1;
assign eem1_n_2 = eem_ch2;
assign eem1_p_2 = ~eem_ch2;
assign eem1_n_3 = eem_ch3;
assign eem1_p_3 = ~eem_ch3;
assign eem1_n_4 = eem_ch4;
assign eem1_p_4 = ~eem_ch4;
assign eem1_n_5 = eem_ch5;
assign eem1_p_5 = ~eem_ch5;
assign eem1_n_6 = eem_ch6;
assign eem1_p_6 = ~eem_ch6;
assign eem1_n_7 = eem_ch7;
assign eem1_p_7 = ~eem_ch7;
wire d_in;
// SB_IO #(
// .IO_STANDARD("SB_LVDS_INPUT"), //"SB_LVCMOS" for output
// .PIN_TYPE(6'd1)
// ) SB_IO (
// .PACKAGE_PIN(eem1_n_2),
// .D_IN_0(d_in)
// );
assign eem_ch0 = counter[3];
assign eem_ch1 = counter[3];
assign eem_ch2 = counter[3];
assign eem_ch3 = counter[3];
assign eem_ch4 = counter[3];
assign eem_ch5 = counter[3];
assign eem_ch6 = counter[3];
assign eem_ch7 = counter[3];
endmodule

18
Syrostan-C.jdebug.user
View File

@ -1,4 +1,5 @@
OpenDocument="user_main.c", FilePath="/home/geekzjk/Desktop/Syrostan-MCU-C/Core/Src/User/user_main.c", Line=14
OpenDocument="fpga.c", FilePath="/home/geekzjk/Desktop/Syrostan-MCU-C/Core/Src/User/fpga.c", Line=43
OpenDocument="main.c", FilePath="/home/geekzjk/Desktop/Syrostan-MCU-C/Core/Src/main.c", Line=63
OpenDocument="stm32f1xx_hal.c", FilePath="/home/geekzjk/Desktop/Syrostan-MCU-C/Drivers/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal.c", Line=372
@ -6,12 +7,13 @@ OpenDocument="stm32f1xx_it.c", FilePath="/home/geekzjk/Desktop/Syrostan-MCU-C/Co
OpenDocument="startup_stm32f103xg.s", FilePath="/home/geekzjk/Desktop/Syrostan-MCU-C/startup_stm32f103xg.s", Line=56
OpenToolbar="Debug", Floating=0, x=0, y=0
OpenWindow="Registers 1", DockArea=RIGHT, x=0, y=0, w=300, h=629, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=0, FilteredItems=[], RefreshRate=1
OpenWindow="Memory 1", DockArea=BOTTOM, x=3, y=0, w=162, h=318, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=0, EditorAddress=0xFC
OpenWindow="Watched Data 1", DockArea=LEFT, x=0, y=1, w=484, h=520, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=0
OpenWindow="Functions", DockArea=LEFT, x=0, y=0, w=484, h=108, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=0
OpenWindow="Data Sampling", DockArea=BOTTOM, x=1, y=0, w=470, h=318, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=0, VisibleTab=0, UniformSampleSpacing=0
OpenWindow="Timeline", DockArea=BOTTOM, x=2, y=0, w=916, h=318, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=1, DataPaneShown=1, PowerPaneShown=1, CodePaneShown=1, PinCursor="Cursor Movable", TimePerDiv="50 ms / Div", TimeStampFormat="Time", DataGraphDrawAsPoints=0, DataGraphLegendShown=1, DataGraphUniformSampleSpacing=0, DataGraphLegendPosition="697;0", PowerGraphDrawAsPoints=0, PowerGraphLegendShown=1, PowerGraphAvgFilterTime=Off, PowerGraphAvgFilterLen=Off, PowerGraphUniformSampleSpacing=0, PowerGraphLegendPosition="734;1", CodeGraphLegendShown=1, CodeGraphLegendPosition="750;0"
OpenWindow="Console", DockArea=BOTTOM, x=0, y=0, w=369, h=318, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=0
OpenWindow="Source Files", DockArea=LEFT, x=0, y=0, w=484, h=179, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=0
OpenWindow="Memory 1", DockArea=BOTTOM, x=2, y=0, w=201, h=318, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=0, EditorAddress=0xFC
OpenWindow="Watched Data 1", DockArea=LEFT, x=0, y=2, w=484, h=211, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=0
OpenWindow="Functions", DockArea=LEFT, x=0, y=1, w=484, h=108, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=0
OpenWindow="Data Sampling", DockArea=BOTTOM, x=0, y=0, w=582, h=318, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=0, VisibleTab=0, UniformSampleSpacing=0
OpenWindow="Timeline", DockArea=BOTTOM, x=1, y=0, w=1135, h=318, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=1, DataPaneShown=1, PowerPaneShown=1, CodePaneShown=1, PinCursor="Cursor Movable", TimePerDiv="50 ms / Div", TimeStampFormat="Time", DataGraphDrawAsPoints=0, DataGraphLegendShown=1, DataGraphUniformSampleSpacing=0, DataGraphLegendPosition="916;0", PowerGraphDrawAsPoints=0, PowerGraphLegendShown=1, PowerGraphAvgFilterTime=Off, PowerGraphAvgFilterLen=Off, PowerGraphUniformSampleSpacing=0, PowerGraphLegendPosition="952;0", CodeGraphLegendShown=1, CodeGraphLegendPosition="968;0"
OpenWindow="Console", DockArea=LEFT, x=0, y=3, w=484, h=128, FilterBarShown=0, TotalValueBarShown=0, ToolBarShown=0
TableHeader="Functions", SortCol="Name", SortOrder="DESCENDING", VisibleCols=["Name";"Address";"Size";"#Insts";"Source"], ColWidths=[1183;100;100;100;203]
TableHeader="Data Sampling Table", SortCol="Index", SortOrder="ASCENDING", VisibleCols=["Index";"Time"], ColWidths=[100;100]
TableHeader="Data Sampling Setup", SortCol="Expression", SortOrder="ASCENDING", VisibleCols=["Expression";"Type";"Value";"Min";"Max";"Average";"# Changes";"Min. Change";"Max. Change"], ColWidths=[100;100;100;100;100;100;100;100;100]
@ -19,7 +21,8 @@ TableHeader="Power Sampling", SortCol="Index", SortOrder="ASCENDING", VisibleCol
TableHeader="Registers 1", SortCol="Name", SortOrder="ASCENDING", VisibleCols=["Name";"Value";"Description"], ColWidths=[100;105;259]
TableHeader="Watched Data 1", SortCol="Expression", SortOrder="ASCENDING", VisibleCols=["Expression";"Value";"Location";"Refresh"], ColWidths=[133;144;100;100]
TableHeader="RegisterSelectionDialog", SortCol="None", SortOrder="ASCENDING", VisibleCols=[], ColWidths=[]
TableHeader="TargetExceptionDialog", SortCol="Name", SortOrder="ASCENDING", VisibleCols=["Name";"Value";"Address";"Description"], ColWidths=[200;100;100;358]
TableHeader="TargetExceptionDialog", SortCol="Name", SortOrder="ASCENDING", VisibleCols=["Name";"Value";"Address";"Description"], ColWidths=[200;100;100;788]
TableHeader="Source Files", SortCol="File", SortOrder="ASCENDING", VisibleCols=["File";"Status";"Size";"#Insts";"Path"], ColWidths=[190;100;100;100;707]
WatchedExpression="spi_test_data", RefreshRate=5, DisplayFormat=DISPLAY_FORMAT_HEX, Window=Watched Data 1
WatchedExpression="enc_mac_address", RefreshRate=5, DisplayFormat=DISPLAY_FORMAT_HEX, Window=Watched Data 1
WatchedExpression="voltages", RefreshRate=5, Window=Watched Data 1
@ -30,3 +33,4 @@ WatchedExpression="fsmc_read_buf", RefreshRate=5, DisplayFormat=DISPLAY_FORMAT_B
WatchedExpression="fsmc_write_buf", RefreshRate=5, Window=Watched Data 1
WatchedExpression="adc_sample", RefreshRate=5, Window=Watched Data 1
WatchedExpression="adc_result", RefreshRate=5, Window=Watched Data 1
WatchedExpression="fsmc_add", RefreshRate=5, Window=Watched Data 1

3
plot_adc.py
View File

@ -7,7 +7,8 @@ import matplotlib.pyplot as plt
ser = serial.Serial('/dev/ttyUSB0', 115200, timeout=None)
# print(ser.name) # check which port was really used
buffer = ser.read(length);
x = [float(x)*ADC_PERIOD for x in range(length)]
# x = [float(x)*ADC_PERIOD for x in range(length)]
x = range(length)
# print(x)
y = []
for i in range(length):