optimize impedance matching for ADC and LVDS (test if 2-layer PCB works fine)

master
Jack-Zheng 2021-08-26 11:45:31 +08:00
parent 312cbf85c4
commit 1acd29d83a
2 changed files with 1976 additions and 1953 deletions

File diff suppressed because it is too large Load Diff

View File

@ -1,4 +1,4 @@
update=Tue Aug 24 16:31:47 2021
update=Thu Aug 26 10:48:36 2021
version=1
last_client=kicad
[general]
@ -33,6 +33,7 @@ TrackWidth2=0.127
TrackWidth3=0.254
TrackWidth4=0.508
TrackWidth5=0.762
TrackWidth6=1.27
ViaDiameter1=0.8
ViaDrill1=0.4
ViaDiameter2=0.5