6454f994af
add libio from ARTIQ
2020-06-03 11:17:28 +08:00
cb24b82e68
rpc: strings
2020-06-01 18:21:04 +08:00
7aa9a95c21
add RPC protocol module (WIP)
2020-06-01 18:02:21 +08:00
15b2b253cf
build for NIST variants
2020-05-14 15:30:50 +08:00
af08b1ad00
update dependencies
2020-05-14 09:28:16 +08:00
1222db56e1
use different user_led to avoid VADJ problems with NIST backplanes
2020-05-14 09:23:43 +08:00
aeefdc862d
update dependencies
2020-05-09 13:48:27 +08:00
7c6f57540e
prevent cargo xbuild from creating sysroot in source tree. Closes #6
2020-05-09 13:21:55 +08:00
b2fe33f6ea
zc706: add support for NIST backplanes
2020-05-07 17:05:00 +08:00
4464b85ab3
move build artifacts out of tree
2020-05-07 13:52:40 +08:00
743b0e198d
cargo: remove outdated runner entry
2020-05-07 13:50:21 +08:00
47261a1d84
update comment/message
2020-05-07 12:43:53 +08:00
d08f4552ab
libdyld: fix pltrel_sz, remove debug output
2020-05-07 01:44:26 +02:00
90faeb6fa2
use new core1 startup mechanism
2020-05-06 22:16:34 +08:00
ae2cee5f7e
also work around mkbootimage potential bug with szl
2020-05-06 17:47:27 +08:00
27466036a7
work around boot.bin/fsbl problems
...
* Use fsbl.elf sent to me by Xilinx tech support. None of the other FSBL images for ZC706, including the official one from 2019.2-zc706-release.tar.xz, appear to work (no UART output, no FPGA DONE).
* Prevent boot.bin creation tool from crashing due to long paths.
2020-05-06 17:38:01 +08:00
7c22b72129
add FSBL startup route
...
Not working (Zynq sucks) and not debuggable (can't get UART output from FSBL even with official binaries...)
2020-05-06 16:53:54 +08:00
1211a6d066
build FSBL
2020-05-06 16:02:44 +08:00
11d839d8a6
update cargoSha256
2020-05-04 23:02:51 +08:00
198985cd6d
runtime: check PL DONE
2020-05-04 22:27:15 +08:00
07efdc6799
szl: cleanup
2020-05-04 22:17:59 +08:00
cbd591b86b
update dependencies
2020-05-03 09:59:24 +08:00
9750bb8aa8
default.nix: change <artiq-fast> syntax
2020-05-03 02:25:19 +02:00
b7695d9313
typo
2020-05-02 11:50:29 +08:00
bca2b3fe50
comms: add comment about closed connection handling
2020-05-02 11:44:10 +08:00
11b58d801d
default.nix: build SD card contents
2020-05-01 11:23:00 +08:00
b7c5a56470
remote_run: fixes
2020-05-01 11:22:45 +08:00
53e1af81b6
add Antmicro Zynq mkbootimage utility
2020-05-01 10:51:13 +08:00
dffbab2707
default.nix: fix szl filenames
2020-05-01 10:48:23 +08:00
a2ea0fbc9f
README: fix formatting
2020-05-01 10:09:31 +08:00
90a19f9986
Merge branch 'master' of git.m-labs.hk:M-Labs/artiq-zynq
2020-05-01 10:08:17 +08:00
2439ba1f88
add impure incremental build process, document
2020-05-01 10:07:38 +08:00
b02c051007
libdyld: fix hash+symtab sizes
2020-05-01 03:20:38 +02:00
92ae487143
update zc706 dependencies
2020-05-01 02:18:52 +02:00
48025339b3
comms: handle connection termination
2020-05-01 02:09:00 +02:00
895a3f47e2
libdyld: refactor
2020-05-01 01:19:10 +02:00
c28c567e72
pure Nix build system
2020-04-30 21:04:28 +08:00
0ebe14c474
sync with zc706 repos
2020-04-30 19:33:57 +08:00
ece60ea898
kernel: remove unused import
2020-04-30 19:33:45 +08:00
656222ff06
libdyld: refactor
2020-04-30 19:23:01 +08:00
22531b14c0
sync with zc706 repos
2020-04-28 19:46:33 +08:00
b123e15b3c
SDRAM loader
2020-04-28 19:07:49 +08:00
21ae674510
kernel: handle no BSS
2020-04-28 19:01:53 +08:00
826368205f
shell.nix: use LLVM tools
2020-04-28 16:22:22 +08:00
848cd28d44
shell.nix: remove openocd/gdb
...
Regular development flow is with remote_run.sh, and those packages are easy to install manually if needed.
Also make the environment complete and usable in nix-shell --pure.
2020-04-28 15:08:41 +08:00
f562ff95c3
use simple RTIO now interface without pinning
2020-04-26 16:10:32 +08:00
44b37aba7d
improve debug messaging
2020-04-26 16:10:09 +08:00
b7eacaeac7
fix RTIO reset
2020-04-26 11:51:21 +08:00
904ee3e730
make LED channels output-only
2020-04-26 11:51:06 +08:00
6fbd6152da
reset RTIO
2020-04-26 09:58:18 +08:00
